Nonvolatile semiconductor memory device which stores multi-value information

Claim 2

A semiconductor memory device having a plurality of memory cells, each memory cell having a floating gate and a control gate, said memory cells are set to a first state by a first write operation by taking electric charge into or out from said floating gate, said memory cells are set to a second state by a second write operation by taking electric charge into or out from said floating gate, each write operation giving a plurality of pluses including a beginning pulse and an ending pulse to said control gate of said memory cell, and a width of said beginning pulse of said first write operation is smaller than that of said ending pulse of said first writing operation.

Claim 3

The semiconductor memory device according to claim 1, wherein said semiconductor memory device is non-volatile memory.

Claim 4

A semiconductor memory device having a plurality of memory cells, each memory cell having a floating gate and a control terminal, said memory cells are set to a first state by a first write operation by taking electric charge into or out from said floating gate, said memory cells are set to a second state by a second write operation by taking electric charge into or out from said floating gate, each write operation giving a plurality of pulses including a beginning pulse to said control terminal of said memory cell, and a width of said beginning pulse of said first write operation is smallest in said plurality of pulses of said first writing operation.

Claim 5

A semiconductor memory device having a plurality of memory cells, each memory cell having a floating gate and a control terminal, said memory cells are set to a first state by a first write operation by taking electric charge into or out from said floating gate, said memory cells are set to a second state by a second write operation by taking electric charge into or out from said floating gate, each write operation giving a plurality of pulses including a beginning pulse to said control terminal of said memory cell, and a width of said beginning pulse of said first write operation is smallest in said plurality of pulses of said first writing operation.

Claim 6

The semiconductor memory device according to claim 3, wherein said semiconductor memory device is non-volatile memory.

Claim 7

A semiconductor memory device having a plurality of memory cells, each memory cell having a floating gate, said memory cells are set to a first state by a first write operation by taking electric charge into or out from said floating gate, said memory cells are set to a second state by a second write operation by taking electric charge into or out from said floating gate, each write operation giving a plurality of pulses to said memory cell, said plurality of pulses including a predetermined pulse and a previous pulse of said predetermined pulse, and a width of said predetermined pulse of said first write operation is greater than that of a previous pulse of said first writing operation.

Claim 8

A semiconductor memory device having a plurality of memory cells, each memory cell having a floating gate, said memory cells are set to a first state by a first write operation by taking electric charge into or out from said floating gate, said memory cells are set to a second state by a second write operation by taking electric charge into or out from said floating gate, each write operation giving a plurality of pulses to said memory cell, said plurality of pulses including a predetermined pulse and a previous pulse of said predetermined pulse, and a width of said predetermined pulse of said first write operation is greater than that of a previous pulse of said first writing operation.

Claim 9

The semiconductor memory device according to claim 5, wherein said semiconductor memory device is non-volatile memory.

Claim 10

A semiconductor memory device according to one of claims 1 to 5, wherein said memory cells are set to a third state by a third write operation by taking electric charge into or out from said floating gate.

Claim 11

The semiconductor memory device according to claim 7, wherein said semiconductor memory device is non-volatile memory.

Claim 12

A semiconductor memory device according to one of claims 1 to 5, wherein said semiconductor memory is operated to have a first period that only said first write operation is operated, and a second period that only said second write operation is operated.

Claim 13

The semiconductor memory device according to claim 9, wherein said semiconductor memory device is non-volatile memory.

Claim 14

A semiconductor memory device according to one of claims 1 to 5, wherein the width of a beginning pulse of said first write operation is different than a width of a beginning pulse of said second write operation.

Claim 15

The semiconductor memory device according to claim 11, wherein said semiconductor memory device is non-volatile memory.

Claim 16

A semiconductor memory device according to one of claims 1 to 5, wherein the height of said plurality of pulses of said first write operation is the same, and the height of said plurality of pulses of said second write operation is the same.

Claim 17

The semiconductor memory device according to claim 13, wherein said semiconductor memory device is non-volatile memory.

Claim 18

A non-volatile semiconductor memory device for making it possible to store four-value information in each of electrically erasable and writable non-volatile memory cells by controlling said memory cell to an erase state, a first write state, a second write state or a third write state, each having a different threshold voltage, comprising: a write control circuit for setting a non-volatile memory cell to the erase state, and controlling each of a first write operation for selectively setting said non-volatile memory cell under the erase state to the first write state, a second write operation for selectively setting said non-volatile memory cell to the second write state after said first write operation, and a third write operation for selectively setting said non-volatile memory cell to the third write state after said second write operation, in a data rewrite operation of said non-volatile memory cell; a write data conversion circuit for generating one-bit write information deciding whether or not said non-volatile memory cell is brought into the first write state by said first write operation, one-bit write information deciding whether or not said non-volatile memory cell is brought into said second write state by said second write operation, and one-bit information deciding whether or not said non-volatile memory cell is brought into the third write state by said third write operation, from two-bit write data given from outside; and a data latch circuit for latching the corresponding write information generated by said write data conversion circuit for each of said first to third write operations by said write control circuit, and selecting whether or not said memory cell is brought into the corresponding write state for each of said first to third write operations, wherein said write control circuit applies a plurality of times a write pulse voltage to said memory cell in each of said first to third write operations, and a beginning write pulse voltage is controlled so that a width of said beginning write pulse voltage is not larger than a width of each of the other write pulse voltages in a write operation and said write operation includes a plurality of pulse voltages having different pulse widths.

Claim 19

A non-volatile semiconductor memory device for making it possible to store four-value information in each of electrically erasable and writable non-volatile memory cells by controlling said memory cell to an erase state, a first write state, a second write state or a third write state, each having a different threshold voltage, comprising: a write control circuit for setting a non-volatile memory cell to the erase state, and controlling each of a first write operation for selectively setting said non-volatile memory cell under the erase state to the first write state, a second write operation for selectively setting said non-volatile memory cell to the second write state after said first write operation, and a third write operation for selectively setting said non-volatile memory cell to the third write state after said second write operation, in a data rewrite operation of said non-volatile memory cell; a write data conversion circuit for generating one-bit write information deciding whether or not said non-volatile memory cell is brought into the first write state by said first write operation, one-bit write information deciding whether or not said non-volatile memory cell is brought into said second write state by said second write operation, and one-bit information deciding whether or not said non-volatile memory cell is brought into the third write state by said third write operation, from two-bit write data given from outside; and a data latch circuit for latching the corresponding write information generated by said write data conversion circuit for each of said first to third write operations by said write control circuit, and selecting whether or not said memory cell is brought into the corresponding write state for each of said first to third write operations, wherein said write control circuit applies a plurality of times a write pulse voltage to said memory cell in each of said first to third write operations, and a beginning write pulse voltage is controlled so that a width of said beginning write pulse voltage is not larger than a width of each of the other write pulse voltages in a write operation and said write operation includes a plurality of pulse voltages having different pulse widths.

Claim 20

The non-volatile semiconductor memory device according to claim 15, further comprising: a read control circuit for controlling a first read operation for selecting said non-volatile, memory cell in accordance with a word line select level between a threshold voltage of said non-volatile memory cell under the erase state and the threshold voltage under said first write state, a second read operation for selecting said non-volatile memory cell in accordance with a word line select level between the threshold voltage of said non-volatile memory cell under the first write state and the threshold voltage under the second write state, and a third read operation for selecting said non-volatile memory cell in accordance with a word line select level between the threshold voltage of said non-volatile memory cell under the second write state and the threshold voltage under the third write state, in a data read operation from said non-volatile memory cell; and a read data conversion circuit for generating two-bit read data representing to which of the erase state, the first write state, the second write state, and the third write state the state of said memory cell as the read objects corresponds, from each one-bit information obtained by each of said first to third read operations by said read control circuit.

Claim 21

The non-volatile semiconductor memory device according to claim 16, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state and the third write state are Vth0, Vth1, Vth2 and Vth3 in order from a higher voltage side, write verify voltages Vv1, Vv2 and Vv3 in the first to third write operations are so set as to satisfy the relation Vth1<Vv1<Vth0, Vth2<Vv2<Vth1 and Vth3<Vv3<Vth2, and the word line select levels Vr1, Vr2 and Vr3 in the first to third read operations are so set as to satisfy the relation Vth1<Vr1<Vth0, Vth2<Vr2<Vth1 and Vth3<Vr3<Vth2.

Claim 22

A non-volatile semiconductor memory device according to claim 16, wherein said memory cell is connected to a bit line and has a sense latch having a memory node thereof connected to said bit line and a switch device selectively connecting said bit line to an input/output line, and said data latch means is a sense latch connected to said bit line selected by said switch device.

Claim 23

The non-volatile semiconductor memory device according to claim 16, wherein said write data conversion circuit sets each write information in each of said first to third write operations to a write non-select level in accordance with the first state of said two-bit write data, sets the write information in said first write operation to a write select level and the write information in each of said the second and third write operations to the write non-select level in accordance with the second state of said two-bit data, sets the write information in each of said first and second write operations to the write select level and the write information in said write operations to the write nonselect level in accordance with the third state of said two-bit write data, and sets the write information in each of said first to third write operations to the select level in accordance with the fourth state of said two-bit write data.

Claim 24

The non-volatile semiconductor memory device according to claim 19, wherein said read data conversion circuit sets said two-bit read data to the first state when three-bit information obtained by said first to third read operations all have a first logic value, sets said two-bit read data to a second state when one-bit information obtained by said first read operation has a second logic value and the two-bit information obtained by said second and third read operations all have the first logic value, sets the two-bit read data to a third state when two-bit information obtained by said first and second read operations have the second logic value and the two-bit information obtained by said third read operation has the first logic value, and sets the two bit read data to a fourth state when the two-bit information obtained by said first to third read operations all have the second logic value.

Claim 25

The non-volatile semiconductor memory device according to claim 19, further comprising: a power source switch circuit for switching the write verify voltage in accordance with each of said first to third write operations.

Claim 26

The non-volatile semiconductor memory device according to claim 15, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state, and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side or the lower side, these threshold voltages are set so that the Hamming distance of bit information represented by the erase state or any of the write states corresponding to the adjacent threshold voltages becomes minimal.

Claim 27

The non-volatile semiconductor memory device according to claim 15, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state, and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side or the lower side, these threshold voltages are set so that the Hamming distance of the bit information represented by the erase state or any of the write states corresponding to the adjacent threshold voltages becomes 1.

Claim 28

The non-volatile semiconductor memory device according to claim 15, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state, and the third write state are Vth0, Vth1, vth2 and Vth3 from the higher side or the lower side, these threshold voltages are set so that the threshold voltages of said memory cell at the time of irradiation of ultra-violet rays become most approximate to Vth0 or Vth3.

Claim 29

The non-volatile semiconductor memory device according to claim 13, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state, and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side or the lower side, these threshold voltages are set so that the Hamming distance of the bit information represented by the erase state or any of the write states corresponding to the adjacent threshold voltages becomes minimal, and the threshold voltage of the memory cell under a thermal equilibrium state is most approximate to Vth0 or Vth3.

Claim 30

A non-volatile semiconductor memory device for making it possible to store four-value information in each of electrically erasable and writable non-volatile memory cells by controlling said memory cell to an erase state, a first write state, a second write state or a third write state, each having a different threshold voltage, comprising: a write control circuit for setting a non-volatile memory cell to the erase state, and controlling each of a first write operation for selectively setting said non-volatile memory cell under the erase state to the first write state, a second write operation for selectively setting said non-volatile memory cell to the second write state after said first write operation, and a third write operation for selectively setting said non-volatile memory cell to the third write state after said second write operation, in a data rewrite operation of said non-volatile memory cell; a write data conversion circuit for generating one-bit write information deciding whether or not said non-volatile memory cell is brought into the first write state by said first write operation, one-bit write information deciding whether or not said non-volatile memory cell is brought into said second write state by said second write operation, and one-bit information deciding whether or not said non-volatile memory cell is brought into the third write state by said third write operation, from two-bit write data given from outside; and a data latch circuit for latching the corresponding write information generated by said write data conversion circuit for each of said first to third write operations by said write control circuit, and selecting whether or not said memory cell is brought into the corresponding write state for each of said first to third write operations, wherein said write control circuit applies a plurality of times a write pulse voltage to said memory cell in each of said first to third write operations, and a beginning write pulse voltage is controlled so that a height of said beginning write pulse, voltage is not larger than a height of each of the other write pulse voltages in a write operation and said write operation includes a plurality of pulse voltages having different pulse heights.

Claim 31

A non-volatile semiconductor memory device for making it possible to store four-value information in each of electrically erasable and writable non-volatile memory cells by controlling said memory cell to an erase state, a first write state, a second write state or a third write state, each having a different threshold voltage, comprising: a write control circuit for setting a non-volatile memory cell to the erase state, and controlling each of a first write operation for selectively setting said non-volatile memory cell under the erase state to the first write state, a second write operation for selectively setting said non-volatile memory cell to the second write state after said first write operation, and a third write operation for selectively setting said non-volatile memory cell to the third write state after said second write operation, in a data rewrite operation of said non-volatile memory cell; a write data conversion circuit for generating one-bit write information deciding whether or not said non-volatile memory cell is brought into the first write state by said first write operation, one-bit write information deciding whether or not said non-volatile memory cell is brought into said second write state by said second write operation, and one-bit information deciding whether or not said non-volatile memory cell is brought into the third write state by said third write operation, from two-bit write data given from outside; and a data latch circuit for latching the corresponding write information generated by said write data conversion circuit for each of said first to third write operations by said write control circuit, and selecting whether or not said memory cell is brought into the corresponding write state for each of said first to third write operations, wherein said write control circuit applies a plurality of times a write pulse voltage to said memory cell in each of said first to third write operations, and a beginning write pulse voltage is controlled so that a height of said beginning write pulse, voltage is not larger than a height of each of the other write pulse voltages in a write operation and said write operation includes a plurality of pulse voltages having different pulse heights.

Claim 32

The non-volatile semiconductor memory device according to claim 26, further comprising: a read control circuit for controlling a first read operation for selecting said non-volatile memory cell in accordance with a word line select level between a threshold voltage of said non-volatile memory cell under the erase state and the threshold voltage under said first write state, a second read operation for selecting said non-volatile memory cell in accordance with a word line select level between the threshold voltage of said non-volatile memory cell under the first write state and the threshold voltage under the second write state, and a third read operation for selecting said non-volatile memory cell in accordance with a word line select level between the threshold voltage of said non-volatile memory cell under the second write state and the threshold voltage under the third write state, in a data read operation from said non-volatile memory cell; and a read data conversion circuit for generating two-bit read data representing to which of the erase state, the first write state, the second write state, and the third write state the state of said memory cell as the read objects corresponds, from each one-bit information obtained by each of said first to third read operations by said read control circuit.

Claim 33

The non-volatile semiconductor memory device according to claim 27, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state and the third write state are Vth0, Vth1, Vth2 and Vth3 in order from a higher voltage side, write verify voltages Vv1, Vv2 and Vv3 in the first to third write operations are so set as to satisfy the relation Vth1<Vv1<Vth0, Vth2<Vv2<Vth1 and Vth3<Vv3<Vth2, and the word line select levels Vr1, Vr2 and Vr3 in the first to third read operations are so set as to satisfy the relation Vth1<Vr1<Vth0, Vth2<Vr2<Vth1 and Vth3<Vr3<Vth2.

Claim 34

The non-volatile semiconductor memory device according to claim 27, wherein said memory cell is connected to a bit line and has a sense latch having a memory node thereof connected to said bit line and a switch device selectively connecting said bit line to an input/output line, and said data latch means is a sense latch connected to said bit line selected by said switch device.

Claim 35

The non-volatile semiconductor memory device according to claim 27, wherein said write data conversion circuit sets each write information in each of said first to third write operations to a write non-select level in accordance with the first state of said two-bit write data, sets the write information in said first write operation to a write select level and the write information in each of said the second and third write operations to the write non-select level in accordance with the second state of said two-bit data, sets the write information in each of said first and second write operations to the write select level and the write information in said write operations to the write nonselect level in accordance with the third state of said two-bit write data, and sets the write information in each of said first to third write operations to the select level in accordance with the fourth state of said two-bit write data.

Claim 36

The non-volatile semiconductor memory device according to claim 30, wherein said read data conversion circuit sets said two-bit read data to the first state when three-bit information obtained by said first to third read operations all have a first logic value, sets said two-bit read data to a second state when one-bit information obtained by said first read operation has a second logic value and the two-bit information obtained by said second and third read operations all have the first logic value, sets the two-bit read data to a third state when two-bit information obtained by said first and second read operations have the second logic value and the two-bit information obtained by said third read operation has the first logic value, and sets the two bit read data to a fourth state when the two-bit information obtained by said first to third read operations all have the second logic value.

Claim 37

The non-volatile semiconductor memory device according to claim 20, further comprising: a power source switch circuit for switching the write verify voltage in accordance with each of said first to third write operations.

Claim 38

The non-volatile semiconductor memory device according to claim 26, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state, and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side or the lower side, these threshold voltages are set so that the Hamming distance of bit information represented by the erase state or any of the write states corresponding to the adjacent threshold voltages becomes minimal.

Claim 39

A non-volatile semiconductor memory device according to claim 26, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state, and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side or the lower side, these threshold voltages are set so that the Hamming distance of the bit information represented by the erase state or any of the write states corresponding to the adjacent threshold voltages becomes 1.

Claim 40

The non-volatile semiconductor memory device according to claim 26, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state, and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side or the lower side, these threshold voltages are set so that the threshold voltages of said memory cell at the time of irradiation of ultra-violet rays become most approximate to Vth0 or Vth3.

Claim 41

The non-volatile semiconductor memory device according to claim 26, wherein, when the threshold voltages of said non-volatile memory cell in the erase state, the first write state, the second write state, and the third write state are Vth0, Vth1, Vth2 and Vth3 from the higher side or the lower side, these threshold voltages are set so that the Hamming distance of the bit information represented by the erase state or any of the write states corresponding to the adjacent threshold voltages becomes minimal, and the threshold voltage of the memory cell under a thermal equilibrium state is most approximate to Vth0 or Vth3.

Claim 42

A semiconductor memory device for storing a plurality of bit informations per memory cell by taking the charge into and out from the floating gate of a plurality of memory cells each having said floating gate and a control gate, comprising: a voltage generation circuit for generating a plurality of voltages; a write circuit for applying a write pulse giving a voltage necessary for taking in and out the charge to said memory cell; and a judgement circuit for serially applying a plurality of voltages to said control gate and judging whether or not said memory cell has a required threshold voltage on the basis of a current value flowing through said memory cell, wherein said write circuit is constituted so that a write operation for giving said write pulse to each of said memory cells and a verify operation for judging whether or not said memory cell has a required threshold voltage, to be executed after said write operation, together constitute one cycle, and when said cycles are repeated a plurality of times and the number of times increases, a pulse width of a beginning write pulse is not larger than a pulse width of each of the other write pulses of said write operation and said write operation includes a plurality of pulse voltages having different pulse widths.

Claim 43

A semiconductor memory device for storing a plurality of bit informations per memory cell by taking the charge into and out from the floating gate of a plurality of memory cells each having said floating gate and a control gate, comprising: a voltage generation circuit for generating a plurality of voltages; a write circuit for applying a write pulse giving a voltage necessary for taking in and out the charge to said memory cell; and a judgement circuit for serially applying a plurality of voltages to said control gate and judging whether or not said memory cell has a required threshold voltage on the basis of a current value flowing through said memory cell, wherein said write circuit is constituted so that a write operation for giving said write pulse to each of said memory cells and a verify operation for judging whether or not said memory cell has a required threshold voltage, to be executed after said write operation, together constitute one cycle, and when said cycles are repeated a plurality of times and the number of times increases, a pulse width of a beginning write pulse is not larger than a pulse width of each of the other write pulses of said write operation and said write operation includes a plurality of pulse voltages having different pulse widths.

Claim 44

A semiconductor memory device according to claim 37, wherein said semiconductor memory device is non-volatile memory.

Claim 45

A semiconductor memory device for storing a plurality of bit information per memory cell, including a plurality of memory cells each having a floating gate and a control gate, for taking charge into and out from said floating gate, comprising: a voltage generation circuit for generating a plurality of voltages; a write circuit for applying a write pulse giving a necessary voltage for taking the charge into and out from said floating gate, to said memory cell; and a judgement circuit for serially applying a plurality of voltages to said control gate, and judging whether or not said memory cell has a required threshold voltage on the basis of a current value flowing through said memory cell, wherein said write circuit is constituted so that a write operation for giving said write pulse to each of said memory cells and a verify operation for judging whether or not said memory cell has a required threshold voltage, to be executed after said write operation, constitute one cycle, and when said cycle is repeated a plurality of times and the number of times increases, a height of a beginning write pulse is not larger than a height of the other write pulses of said write operation and said write operation includes a plurality of pulse voltages having different pulse heights.

Claim 46

A semiconductor memory device for storing a plurality of bit information per memory cell, including a plurality of memory cells each having a floating gate and a control gate, for taking charge into and out from said floating gate, comprising: a voltage generation circuit for generating a plurality of voltages; a write circuit for applying a write pulse giving a necessary voltage for taking the charge into and out from said floating gate, to said memory cell; and a judgement circuit for serially applying a plurality of voltages to said control gate, and judging whether or not said memory cell has a required threshold voltage on the basis of a current value flowing through said memory cell, wherein said write circuit is constituted so that a write operation for giving said write pulse to each of said memory cells and a verify operation for judging whether or not said memory cell has a required threshold voltage, to be executed after said write operation, constitute one cycle, and when said cycle is repeated a plurality of times and the number of times increases, a height of a beginning write pulse is not larger than a height of the other write pulses of said write operation and said write operation includes a plurality of pulse voltages having different pulse heights.

Claim 47

The semiconductor memory device according to claim 39, wherein said semiconductor memory device is non-volatile memory.