US5365486A
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Method and circuitry for refreshing a flash electrically erasable, programmable read only memory
Assignee: Texas Instruments Inc
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Filing: 1992-12-16
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Granted: 1994-11-15
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Expires: 2012-12-16
Abstract
Abstract A method and apparatus for flash EEPROM refresh is provided in which the control gate of a particular memory cell is read at an elevated control gate voltage (42). It is next determined whether the cell has been programmed (44). If the cell has been programmed, then the next memory cell is read (46). If it is initially determined that the cell has not been programmed (44), then the particular memory cell is read at a lowered control gate voltage (48). It is then finally determined whether the cell has been programmed (50). If it is determined that the cell has not been programmed, then the next cell is read (46). If it is determined that the cell has been programmed (50), then the memory is refreshed (52). After refresh, the next memory cell is read (46).
Inventors
- 👤 John F. Schreck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 01:06
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3431; G11C16/10
Claims Analysis
Total Claims: 52
Claim 1
Independent Claim
151 words
A method of refreshing a flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising the steps of: reading a particular memory cell at an elevated control gate voltage; making an initial determination of whether the particular memory cell has been programmed; if the initial determination is that the particular memory cell has been programmed, performing said method on another memory cell; if the initial determination is that the particular memory cell has not been programmed, reading the particular memory cell at a lowered control gate voltage; making a final determination of whether the particular memory cell has been programmed; if the final determination is that the particular memory cell has not been programmed, performing said method on another memory cell; if the final determination is that the particular memory cell has been programmed, refreshing the particular memory cell; and performing said method on another memory cell.
Claim 2
Independent Claim
151 words
A method of refreshing a flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising the steps of: reading a particular memory cell at an elevated control gate voltage; making an initial determination of whether the particular memory cell has been programmed; if the initial determination is that the particular memory cell has been programmed, performing said method on another memory cell; if the initial determination is that the particular memory cell has not been programmed, reading the particular memory cell at a lowered control gate voltage; making a final determination of whether the particular memory cell has been programmed; if the final determination is that the particular memory cell has not been programmed, performing said method on another memory cell; if the final determination is that the particular memory cell has been programmed, refreshing the particular memory cell; and performing said method on another memory cell.
Claim 3
Dependent Claim
39 words
The method of claim 1, wherein said step of making an initial determination comprises determining whether the particular memory cell conducts at the elevated control gate voltage, conduction indicating initially that the particular memory cell has not been programmed.
Claim 4
Dependent Claim
32 words
The method of claim 2, wherein said step of making a final determination comprises determining whether the particular memory cell conducts, conduction indicating that the particular memory cell has not been programmed.
Claim 5
Dependent Claim
32 words
The method of claim 1, wherein said step of making a final determination comprises determining whether the particular memory cell conducts, conduction indicating that the particular memory cell has not been programmed.
Claim 6
Dependent Claim
20 words
The method of claim 1, wherein said step of refreshing comprises pulsing the particular memory cell with a restoration pulse.
Claim 7
Dependent Claim
21 words
The method of claim 5, wherein said restoration pulse has a smaller pulse width than the width of a programming pulse.
Claim 8
Dependent Claim
55 words
The method of claim 1, wherein the memory cells are divided into sectors, and further comprising the steps of: counting the number of erase cycles performed in sectors electrically associated with a particular sector; and performing said method on cells within the particular sector in response to said step of counting reaching a predetermined number.
Claim 9
Independent Claim
150 words
A method of refreshing a flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising the steps of: reading a particular memory cell at a lowered control gate voltage; making an initial determination of whether the particular memory cell has been programmed; if the initial determination is that the particular memory cell has not been programmed, performing said method on another memory cell; if the initial determination is that the particular memory cell has been programmed, reading the particular memory cell at an elevated control gate voltage; making a final determination of whether the particular memory cell is still programmed; if the final determination is that the particular memory cell is still programmed, performing said method on another memory cell; if the final determination is that the particular memory cell has been disturbed, refreshing the particular memory cell; and performing said method on another memory cell.
Claim 10
Independent Claim
150 words
A method of refreshing a flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising the steps of: reading a particular memory cell at a lowered control gate voltage; making an initial determination of whether the particular memory cell has been programmed; if the initial determination is that the particular memory cell has not been programmed, performing said method on another memory cell; if the initial determination is that the particular memory cell has been programmed, reading the particular memory cell at an elevated control gate voltage; making a final determination of whether the particular memory cell is still programmed; if the final determination is that the particular memory cell is still programmed, performing said method on another memory cell; if the final determination is that the particular memory cell has been disturbed, refreshing the particular memory cell; and performing said method on another memory cell.
Claim 11
Dependent Claim
38 words
The method of claim 8, wherein said step of making an initial determination comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been programmed.
Claim 12
Dependent Claim
31 words
The method of claim 9, wherein said step of making a final determination comprises determining whether the particular memory cell conducts, conduction indicating that the particular memory cell has been disturbed.
Claim 13
Dependent Claim
31 words
The method of claim 8, wherein said step of making a final determination comprises determining whether the particular memory cell conducts, conduction indicating that the particular memory cell has been disturbed.
Claim 14
Dependent Claim
20 words
The method of claim 8, wherein said step of refreshing comprises pulsing the particular memory cell with a restoration pulse.
Claim 15
Dependent Claim
21 words
The method of claim 12, wherein said restoration pulse has a smaller pulse width than the width of a programming pulse.
Claim 16
Dependent Claim
55 words
The method of claim 8, wherein the memory cells are divided into sectors, and further comprising the steps of: counting the number of erase cycles performed in sectors electrically associated with a particular sector; and performing said method on cells within the particular sector in response to said step of counting reaching a predetermined number.
Claim 17
Independent Claim
248 words
A method of refreshing a flash electrically erasable, programmable read only memory having a plurality of memory cells grouped in sectors of said cells, comprising the steps of: determining whether a particular memory cell has been programmed or erased; if the state of a particular memory cell is programmed, performing said method on another memory cell; if the state of a particular memory cell is erased, performing the steps of: reading the particular memory cell at a lowered control gate voltage; making a determination of whether the particular memory cell is still erased; if the determination is that the particular memory cell is still erased, performing said method on another memory cell; if the determination is that the particular memory cell has been disturbed, erasing the sector in which the particular memory cell resides; and reprogramming said sector in which the particular memory cell resides and if there has been no erasing and reprogramming after all erased cells have been processed, performing the steps of: reading a particular reprogrammed cell at an elevated control gate voltage; making a determination of whether the particular memory cell is still reprogrammed; if the determination is that the particular memory cell is still reprogrammed, performing said step of reading at an elevated control voltage on another reprogrammed memory cell; if the determination is that the particular memory cell has been disturbed, refreshing the particular memory cell; and performing said step of reading at an elevated control voltage on another reprogrammed memory cell.
Claim 18
Independent Claim
248 words
A method of refreshing a flash electrically erasable, programmable read only memory having a plurality of memory cells grouped in sectors of said cells, comprising the steps of: determining whether a particular memory cell has been programmed or erased; if the state of a particular memory cell is programmed, performing said method on another memory cell; if the state of a particular memory cell is erased, performing the steps of: reading the particular memory cell at a lowered control gate voltage; making a determination of whether the particular memory cell is still erased; if the determination is that the particular memory cell is still erased, performing said method on another memory cell; if the determination is that the particular memory cell has been disturbed, erasing the sector in which the particular memory cell resides; and reprogramming said sector in which the particular memory cell resides and if there has been no erasing and reprogramming after all erased cells have been processed, performing the steps of: reading a particular reprogrammed cell at an elevated control gate voltage; making a determination of whether the particular memory cell is still reprogrammed; if the determination is that the particular memory cell is still reprogrammed, performing said step of reading at an elevated control voltage on another reprogrammed memory cell; if the determination is that the particular memory cell has been disturbed, refreshing the particular memory cell; and performing said step of reading at an elevated control voltage on another reprogrammed memory cell.
Claim 19
Dependent Claim
46 words
The method of claim 15, and further comprising the steps of: storing the state of each memory cell after determining the state of each cell; and storing the states of memory cells not yet determined after determining that a particular erased memory cell has been disturbed.
Claim 20
Dependent Claim
18 words
The method of claim 15, and further comprising the step of storing the states of all memory cells.
Claim 21
Dependent Claim
29 words
The method of claim 15, and further comprising the step of storing the states of all memory cells after determining that a particular erased memory cell has been disturbed.
Claim 22
Dependent Claim
52 words
The method of claim 15, wherein said step of determining whether a particular memory cell has been programmed or erased comprises reading the particular cell at a control gate voltage that is high enough to ensure conduction through disturbed erased cells and low enough to ensure no conduction through disturbed programmed cells.
Claim 23
Dependent Claim
44 words
The method of claim 15, wherein said step of making a determination of whether the particular cell is still programmed comprises determining whether the particular memory cell conducts at the elevated control gate voltage, conduction indicating that the particular memory cell has been disturbed.
Claim 24
Dependent Claim
45 words
The method of claim 20, wherein said step of making a determination of whether the particular cell is still erased comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been disturbed.
Claim 25
Dependent Claim
45 words
The method of claim 15, wherein said step of making a determination of whether the particular cell is still erased comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been disturbed.
Claim 26
Dependent Claim
20 words
The method of claim 15, wherein said step of refreshing comprises pulsing the particular memory cell with a restoration pulse.
Claim 27
Dependent Claim
21 words
The method of claim 23, wherein the restoration pulse has a smaller pulse width than the width of a programing pulse.
Claim 28
Dependent Claim
46 words
The method of claim 15, further comprising the steps of: counting the number of erase cycles performed in sectors electrically associated with a particular sector; and performing said method on cells within the particular sector in response to said step of counting reaching a predetermined number.
Claim 29
Independent Claim
209 words
A method of refreshing a flash electrically erasable, programmable read only memory having a plurality of memory cells grouped in sectors of said cells, comprising the steps of: determining whether a particular memory cell has been programmed or erased; if the state of a particular memory cell is programmed, performing the steps of: reading the particular memory cell at an elevated control gate voltage; making a determination of whether the particular memory cell is still programmed; if the determination is that the particular memory cell is still programmed, performing said method on another memory cell; if the determination is that the particular memory cell has been disturbed, refreshing the particular memory cell; and performing said method on another memory cell; and if the state of the particular memory cell is erased, performing the steps of: reading the particular programmed cell at a lowered control gate voltage; making a determination of whether the particular memory cell is still erased; if the determination is that the particular memory cell is still erased, performing said step on another memory cell; if the determination is that the particular memory cell has been disturbed, erasing the sector in which the memory cell resides; and reprogramming said sector in which the particular memory cell resides.
Claim 30
Independent Claim
209 words
A method of refreshing a flash electrically erasable, programmable read only memory having a plurality of memory cells grouped in sectors of said cells, comprising the steps of: determining whether a particular memory cell has been programmed or erased; if the state of a particular memory cell is programmed, performing the steps of: reading the particular memory cell at an elevated control gate voltage; making a determination of whether the particular memory cell is still programmed; if the determination is that the particular memory cell is still programmed, performing said method on another memory cell; if the determination is that the particular memory cell has been disturbed, refreshing the particular memory cell; and performing said method on another memory cell; and if the state of the particular memory cell is erased, performing the steps of: reading the particular programmed cell at a lowered control gate voltage; making a determination of whether the particular memory cell is still erased; if the determination is that the particular memory cell is still erased, performing said step on another memory cell; if the determination is that the particular memory cell has been disturbed, erasing the sector in which the memory cell resides; and reprogramming said sector in which the particular memory cell resides.
Claim 31
Dependent Claim
46 words
The method of claim 26, and further comprising the steps of: storing the state of each memory cell after determining the state of each cell; and storing the states of memory cells not yet determined after determining that a particular erased memory cell has been disturbed.
Claim 32
Dependent Claim
18 words
The method of claim 26, and further comprising the step of storing the states of all memory cells.
Claim 33
Dependent Claim
29 words
The method of claim 26, and further comprising the step of storing the states of all memory cells after determining that a particular erased memory cell has been disturbed.
Claim 34
Dependent Claim
52 words
The method of claim 26, wherein said step of determining whether a particular memory cell has been programmed or erased comprises reading the particular cell at a control gate voltage that is high enough to ensure conduction through disturbed erased cells and low enough to ensure no conduction through disturbed programmed cells.
Claim 35
Dependent Claim
44 words
The method of claim 26, wherein said step of making a determination of whether the particular cell is still programmed comprises determining whether the particular memory cell conducts at the elevated control gate voltage, conduction indicating that the particular memory cell has been disturbed.
Claim 36
Dependent Claim
45 words
The method of claim 31, wherein said step of making a determination of whether the particular cell is still erased comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been disturbed.
Claim 37
Dependent Claim
45 words
The method of claim 26, wherein said step of making a determination of whether the particular cell is still erased comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been disturbed.
Claim 38
Dependent Claim
20 words
The method of claim 26, wherein said step of refreshing comprises pulsing the particular memory cell with a restoration pulse.
Claim 39
Dependent Claim
21 words
The method of claim 34, wherein the restoration pulse has a smaller pulse width than the width of a programing pulse.
Claim 40
Dependent Claim
46 words
The method of claim 26 further comprising the steps of: counting the number of erase cycles performed in sectors electrically associated with a particular sector; and performing said method on cells within the particular sector in response to said step of counting reaching a predetermined number.
Claim 41
Dependent Claim
168 words
A flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising: a plurality of sectors, each of said sectors including a plurality of memory cells, each of said memory cells including a control gate, and said memory cells operable to conduct if erased and not conduct if programmed; a row decoder coupled to said sectors, said row decoder operable to generate an elevated and a lowered control gate voltage; a column decoder coupled to said sectors; a read/write/erase circuit coupled to said row decoder and said column decoder, said row decoder, said column decoder, and said read/write/erase circuit for reading, programing, and erasing particular memory cells within said sectors; circuitry for causing said memory cells to be read at said elevated control gate voltage; circuitry for causing those memory cells which conduct at said elevated control gate voltage to be read at said lowered control gate voltage; and circuitry for refreshing those memory cells which do not conduct at said lowered control gate voltage.
Claim 42
Dependent Claim
168 words
A flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising: a plurality of sectors, each of said sectors including a plurality of memory cells, each of said memory cells including a control gate, and said memory cells operable to conduct if erased and not conduct if programmed; a row decoder coupled to said sectors, said row decoder operable to generate an elevated and a lowered control gate voltage; a column decoder coupled to said sectors; a read/write/erase circuit coupled to said row decoder and said column decoder, said row decoder, said column decoder, and said read/write/erase circuit for reading, programing, and erasing particular memory cells within said sectors; circuitry for causing said memory cells to be read at said elevated control gate voltage; circuitry for causing those memory cells which conduct at said elevated control gate voltage to be read at said lowered control gate voltage; and circuitry for refreshing those memory cells which do not conduct at said lowered control gate voltage.
Claim 43
Dependent Claim
18 words
The circuit of claim 37, wherein said circuitry for refreshing is operable to cause programming through restoration pulses.
Claim 44
Dependent Claim
21 words
The circuit of claim 38, wherein said restoration pulses are of smaller pulse width than the width of a programming pulse.
Claim 45
Dependent Claim
59 words
The circuit of claim 37, and further comprising counting circuitry for counting the number of erase cycles performed in sectors electrically associated with a particular sector, such that said circuitry for causing reading at said elevated and lowered control gate voltages, and said circuitry for refreshing are enabled in response to said counting circuitry counting to a predetermined number.
Claim 46
Dependent Claim
257 words
A flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising: a memory for storing the state of said memory cells; a plurality of sectors, each of said sectors including a plurality of memory cells, each of said memory cells including a control gate, and said memory cells operable to conduct if erased and not conduct if programmed; a row decoder coupled to said sectors, said row decoder operable to generate an elevated control gate voltage, a lowered control gate voltage, and a determination control gate voltage; a column decoder coupled to said sectors; a read/write/erase circuit coupled to said row decoder and said column decoder, said row decoder, said column decoder, and said read/write/erase circuit for reading, programming, and erasing particular memory cells within said sectors; circuitry for storing the state of particular memory cells after being read at said determination control gate voltage; circuitry for accessing said random access memory and reading the state of each memory cell; circuitry for causing those memory cells which have been programmed to be read at said elevated control gate voltage; circuitry for refreshing those memory cells which have been programmed and which conduct at said elevated control gate voltage; circuitry for causing those memory cells which have been erased to be read at said lowered control gate voltage; circuitry for causing erasure of the sectors in which memory cells reside which have been erased and which do not conduct at said lowered control gate voltage; and circuitry for causing reprogramming of the erased sectors.
Claim 47
Dependent Claim
257 words
A flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising: a memory for storing the state of said memory cells; a plurality of sectors, each of said sectors including a plurality of memory cells, each of said memory cells including a control gate, and said memory cells operable to conduct if erased and not conduct if programmed; a row decoder coupled to said sectors, said row decoder operable to generate an elevated control gate voltage, a lowered control gate voltage, and a determination control gate voltage; a column decoder coupled to said sectors; a read/write/erase circuit coupled to said row decoder and said column decoder, said row decoder, said column decoder, and said read/write/erase circuit for reading, programming, and erasing particular memory cells within said sectors; circuitry for storing the state of particular memory cells after being read at said determination control gate voltage; circuitry for accessing said random access memory and reading the state of each memory cell; circuitry for causing those memory cells which have been programmed to be read at said elevated control gate voltage; circuitry for refreshing those memory cells which have been programmed and which conduct at said elevated control gate voltage; circuitry for causing those memory cells which have been erased to be read at said lowered control gate voltage; circuitry for causing erasure of the sectors in which memory cells reside which have been erased and which do not conduct at said lowered control gate voltage; and circuitry for causing reprogramming of the erased sectors.
Claim 48
Dependent Claim
18 words
The circuit of claim 41, wherein said circuitry for refreshing is operable to cause programing through restoration pulses.
Claim 49
Dependent Claim
21 words
The circuit of claim 42, wherein said restoration pulses are of smaller pulse width than the width of a programming pulse.
Claim 50
Dependent Claim
59 words
The circuit of claim 41, and further comprising counting circuitry for counting the number of erase cycles performed in sectors electrically associated with a particular sector, such that said circuitry for causing reading at said elevated and lowered control gate voltages, and said circuitry for refreshing are enabled in response to said counting circuitry counting to a predetermined number.
Claim 51
Dependent Claim
14 words
The circuit of claim 41, wherein said memory is on-chip with said memory cells.
Claim 52
Dependent Claim
14 words
The circuit of claim 41, wherein said memory is off-chip from said memory cells.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1997-11-14 | 1998-05-16 | 1998-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-14 | 2002-05-16 | 2002-11-15 | $3760.00 | Window Closed / Lapsed |
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