Method and circuitry for refreshing a flash electrically erasable, programmable read only memory

Claim 3

The method of claim 1, wherein said step of making an initial determination comprises determining whether the particular memory cell conducts at the elevated control gate voltage, conduction indicating initially that the particular memory cell has not been programmed.

Claim 4

The method of claim 2, wherein said step of making a final determination comprises determining whether the particular memory cell conducts, conduction indicating that the particular memory cell has not been programmed.

Claim 5

The method of claim 1, wherein said step of making a final determination comprises determining whether the particular memory cell conducts, conduction indicating that the particular memory cell has not been programmed.

Claim 6

The method of claim 1, wherein said step of refreshing comprises pulsing the particular memory cell with a restoration pulse.

Claim 7

The method of claim 5, wherein said restoration pulse has a smaller pulse width than the width of a programming pulse.

Claim 8

The method of claim 1, wherein the memory cells are divided into sectors, and further comprising the steps of: counting the number of erase cycles performed in sectors electrically associated with a particular sector; and performing said method on cells within the particular sector in response to said step of counting reaching a predetermined number.

Claim 11

The method of claim 8, wherein said step of making an initial determination comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been programmed.

Claim 12

The method of claim 9, wherein said step of making a final determination comprises determining whether the particular memory cell conducts, conduction indicating that the particular memory cell has been disturbed.

Claim 13

The method of claim 8, wherein said step of making a final determination comprises determining whether the particular memory cell conducts, conduction indicating that the particular memory cell has been disturbed.

Claim 14

The method of claim 8, wherein said step of refreshing comprises pulsing the particular memory cell with a restoration pulse.

Claim 15

The method of claim 12, wherein said restoration pulse has a smaller pulse width than the width of a programming pulse.

Claim 16

The method of claim 8, wherein the memory cells are divided into sectors, and further comprising the steps of: counting the number of erase cycles performed in sectors electrically associated with a particular sector; and performing said method on cells within the particular sector in response to said step of counting reaching a predetermined number.

Claim 19

The method of claim 15, and further comprising the steps of: storing the state of each memory cell after determining the state of each cell; and storing the states of memory cells not yet determined after determining that a particular erased memory cell has been disturbed.

Claim 20

The method of claim 15, and further comprising the step of storing the states of all memory cells.

Claim 21

The method of claim 15, and further comprising the step of storing the states of all memory cells after determining that a particular erased memory cell has been disturbed.

Claim 22

The method of claim 15, wherein said step of determining whether a particular memory cell has been programmed or erased comprises reading the particular cell at a control gate voltage that is high enough to ensure conduction through disturbed erased cells and low enough to ensure no conduction through disturbed programmed cells.

Claim 23

The method of claim 15, wherein said step of making a determination of whether the particular cell is still programmed comprises determining whether the particular memory cell conducts at the elevated control gate voltage, conduction indicating that the particular memory cell has been disturbed.

Claim 24

The method of claim 20, wherein said step of making a determination of whether the particular cell is still erased comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been disturbed.

Claim 25

The method of claim 15, wherein said step of making a determination of whether the particular cell is still erased comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been disturbed.

Claim 26

The method of claim 15, wherein said step of refreshing comprises pulsing the particular memory cell with a restoration pulse.

Claim 27

The method of claim 23, wherein the restoration pulse has a smaller pulse width than the width of a programing pulse.

Claim 28

The method of claim 15, further comprising the steps of: counting the number of erase cycles performed in sectors electrically associated with a particular sector; and performing said method on cells within the particular sector in response to said step of counting reaching a predetermined number.

Claim 31

The method of claim 26, and further comprising the steps of: storing the state of each memory cell after determining the state of each cell; and storing the states of memory cells not yet determined after determining that a particular erased memory cell has been disturbed.

Claim 32

The method of claim 26, and further comprising the step of storing the states of all memory cells.

Claim 33

The method of claim 26, and further comprising the step of storing the states of all memory cells after determining that a particular erased memory cell has been disturbed.

Claim 34

The method of claim 26, wherein said step of determining whether a particular memory cell has been programmed or erased comprises reading the particular cell at a control gate voltage that is high enough to ensure conduction through disturbed erased cells and low enough to ensure no conduction through disturbed programmed cells.

Claim 35

The method of claim 26, wherein said step of making a determination of whether the particular cell is still programmed comprises determining whether the particular memory cell conducts at the elevated control gate voltage, conduction indicating that the particular memory cell has been disturbed.

Claim 36

The method of claim 31, wherein said step of making a determination of whether the particular cell is still erased comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been disturbed.

Claim 37

The method of claim 26, wherein said step of making a determination of whether the particular cell is still erased comprises determining whether the particular memory cell conducts at the lowered control gate voltage, conduction indicating that the particular memory cell has not been disturbed.

Claim 38

The method of claim 26, wherein said step of refreshing comprises pulsing the particular memory cell with a restoration pulse.

Claim 39

The method of claim 34, wherein the restoration pulse has a smaller pulse width than the width of a programing pulse.

Claim 40

The method of claim 26 further comprising the steps of: counting the number of erase cycles performed in sectors electrically associated with a particular sector; and performing said method on cells within the particular sector in response to said step of counting reaching a predetermined number.

Claim 41

A flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising: a plurality of sectors, each of said sectors including a plurality of memory cells, each of said memory cells including a control gate, and said memory cells operable to conduct if erased and not conduct if programmed; a row decoder coupled to said sectors, said row decoder operable to generate an elevated and a lowered control gate voltage; a column decoder coupled to said sectors; a read/write/erase circuit coupled to said row decoder and said column decoder, said row decoder, said column decoder, and said read/write/erase circuit for reading, programing, and erasing particular memory cells within said sectors; circuitry for causing said memory cells to be read at said elevated control gate voltage; circuitry for causing those memory cells which conduct at said elevated control gate voltage to be read at said lowered control gate voltage; and circuitry for refreshing those memory cells which do not conduct at said lowered control gate voltage.

Claim 42

A flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising: a plurality of sectors, each of said sectors including a plurality of memory cells, each of said memory cells including a control gate, and said memory cells operable to conduct if erased and not conduct if programmed; a row decoder coupled to said sectors, said row decoder operable to generate an elevated and a lowered control gate voltage; a column decoder coupled to said sectors; a read/write/erase circuit coupled to said row decoder and said column decoder, said row decoder, said column decoder, and said read/write/erase circuit for reading, programing, and erasing particular memory cells within said sectors; circuitry for causing said memory cells to be read at said elevated control gate voltage; circuitry for causing those memory cells which conduct at said elevated control gate voltage to be read at said lowered control gate voltage; and circuitry for refreshing those memory cells which do not conduct at said lowered control gate voltage.

Claim 43

The circuit of claim 37, wherein said circuitry for refreshing is operable to cause programming through restoration pulses.

Claim 44

The circuit of claim 38, wherein said restoration pulses are of smaller pulse width than the width of a programming pulse.

Claim 45

The circuit of claim 37, and further comprising counting circuitry for counting the number of erase cycles performed in sectors electrically associated with a particular sector, such that said circuitry for causing reading at said elevated and lowered control gate voltages, and said circuitry for refreshing are enabled in response to said counting circuitry counting to a predetermined number.

Claim 46

A flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising: a memory for storing the state of said memory cells; a plurality of sectors, each of said sectors including a plurality of memory cells, each of said memory cells including a control gate, and said memory cells operable to conduct if erased and not conduct if programmed; a row decoder coupled to said sectors, said row decoder operable to generate an elevated control gate voltage, a lowered control gate voltage, and a determination control gate voltage; a column decoder coupled to said sectors; a read/write/erase circuit coupled to said row decoder and said column decoder, said row decoder, said column decoder, and said read/write/erase circuit for reading, programming, and erasing particular memory cells within said sectors; circuitry for storing the state of particular memory cells after being read at said determination control gate voltage; circuitry for accessing said random access memory and reading the state of each memory cell; circuitry for causing those memory cells which have been programmed to be read at said elevated control gate voltage; circuitry for refreshing those memory cells which have been programmed and which conduct at said elevated control gate voltage; circuitry for causing those memory cells which have been erased to be read at said lowered control gate voltage; circuitry for causing erasure of the sectors in which memory cells reside which have been erased and which do not conduct at said lowered control gate voltage; and circuitry for causing reprogramming of the erased sectors.

Claim 47

A flash electrically erasable, programmable read only memory having a plurality of memory cells, comprising: a memory for storing the state of said memory cells; a plurality of sectors, each of said sectors including a plurality of memory cells, each of said memory cells including a control gate, and said memory cells operable to conduct if erased and not conduct if programmed; a row decoder coupled to said sectors, said row decoder operable to generate an elevated control gate voltage, a lowered control gate voltage, and a determination control gate voltage; a column decoder coupled to said sectors; a read/write/erase circuit coupled to said row decoder and said column decoder, said row decoder, said column decoder, and said read/write/erase circuit for reading, programming, and erasing particular memory cells within said sectors; circuitry for storing the state of particular memory cells after being read at said determination control gate voltage; circuitry for accessing said random access memory and reading the state of each memory cell; circuitry for causing those memory cells which have been programmed to be read at said elevated control gate voltage; circuitry for refreshing those memory cells which have been programmed and which conduct at said elevated control gate voltage; circuitry for causing those memory cells which have been erased to be read at said lowered control gate voltage; circuitry for causing erasure of the sectors in which memory cells reside which have been erased and which do not conduct at said lowered control gate voltage; and circuitry for causing reprogramming of the erased sectors.

Claim 48

The circuit of claim 41, wherein said circuitry for refreshing is operable to cause programing through restoration pulses.

Claim 49

The circuit of claim 42, wherein said restoration pulses are of smaller pulse width than the width of a programming pulse.

Claim 50

The circuit of claim 41, and further comprising counting circuitry for counting the number of erase cycles performed in sectors electrically associated with a particular sector, such that said circuitry for causing reading at said elevated and lowered control gate voltages, and said circuitry for refreshing are enabled in response to said counting circuitry counting to a predetermined number.

Claim 51

The circuit of claim 41, wherein said memory is on-chip with said memory cells.

Claim 52

The circuit of claim 41, wherein said memory is off-chip from said memory cells.