Semiconductor memory

Claim 2

A semiconductor memory comprising: a semiconductor memory circuit which requires data refresh; a first counter for counting the number of times the semiconductor memory circuit requires data refresh operations; a second counter for counting the number of times the semiconductor memory circuit has performed the data refresh operations; a counter comparator for comparing an output of the first counter and an output of the second counter with each other; and control means for receiving a comparison signal output from the counter comparator, as well as a refresh request signal externally supplied, and for outputting a refresh clock signal to the semiconductor memory circuit in response to the comparison signal and the refresh request signal.

Claim 3

A semiconductor memory according to claim 1, wherein the control means comprises: a refresh request controller for receiving the comparison signal of the counter comparator and the externally-supplied refresh request signal, the refresh request controller being controlled to be in a disabled state in accordance with a comparison signal which is output from the control means when the output of the first counter and the output of the second counter coincide with each other, and controlled to be in an enabled state in accordance with a comparison signal which is output from the control means when the output of the first counter and the output of the second counter do not coincide with each other, the refresh request controller in the enabled state accepting the externally-supplied refresh request signal and outputting an internal refresh request signal; and a refresh clock generator for receiving the internal refresh signal output from the refresh request controller and outputting the refresh clock signal.

Claim 4

A semiconductor memory according to claim 2, wherein the refresh clock generator receives the internal refresh request signal and outputs a clock signal, to be used for counting, to the second counter.

Claim 5

A semiconductor memory according to claim 1, wherein a latch circuit, for latching the comparison signal of the counter comparator for a predetermined period of time, is provided on the output side of the counter comparator.

Claim 6

A data refresh system for a semiconductor memory requiring data refresh, comprising: first counting means for counting the number of times the semiconductor memory requires data refresh and for generating an output indicating the number of times data refresh should be performed on the semiconductor memory; second counting means for counting the number of times data refresh has been performed on the semiconductor memory and for generating an output indicating the number of times data refresh has been performed on the semiconductor memory; comparator means for comparing the output of the first counting means with the output of the second counting means and for generating a comparison signal when the output of the first counting means equals the output of the second counting means; and control means for receiving the comparison signal output from the comparator means, a refresh request signal externally supplied, and for outputting a refresh signal to perform data refresh on the semiconductor memory.

Claim 7

A data refresh system for a semiconductor memory requiring data refresh, comprising: first counting means for counting the number of times the semiconductor memory requires data refresh and for generating an output indicating the number of times data refresh should be performed on the semiconductor memory; second counting means for counting the number of times data refresh has been performed on the semiconductor memory and for generating an output indicating the number of times data refresh has been performed on the semiconductor memory; comparator means for comparing the output of the first counting means with the output of the second counting means and for generating a comparison signal when the output of the first counting means equals the output of the second counting means; and control means for receiving the comparison signal output from the comparator means, a refresh request signal externally supplied, and for outputting a refresh signal to perform data refresh on the semiconductor memory.

Claim 8

A data refresh system according to claim 5 further comprising, a latch circuit for latching the comparison signal for a predetermined period of time provided on the output side of the comparator means.