FIFO buffer controller

Claim 2

A control circuit for a FIFO (first in first out) memory circuit for providing address information to FIFO memory means having an address field of n bits, said control circuit comprising: a first means for providing a first binary signal having n+1 bits; a second means for providing a second binary signal having n+1 bits; first comparator means for comparing the most significant bit of said first signal with the most significant bit of said second signal and producing a first control signal indicative of said comparison; second comparator means for comparing the n least significant bits of said first signal with the n least significant bits of said second signal, and producing a second control signal indicative of said comparison; logic means, responsive to said first control signal and said second control signal, for producing an indicator signal of said memory circuit being full or not full.

Claim 3

The control circuit of claim 1 wherein said first means is a counter means and wherein said second means is a counter means.

Claim 4

The control circuit of claim 1 wherein said first means is a counter means and wherein said second means is a counter means.

Claim 5

The control circuit of claim 3 further including a multiplexer means for receiving both said first signal and said second signal and selecting either said first or said second signal as its output whereby the output of said multiplexer, less the most significant bit, is used to address said FIFO memory means.

Claim 6

A control circuit for a FIFO (first in first out) memory circuit for providing address information to a FIFO memory means having an address field of n bits, said control circuit comprising: first counter means for providing a first signal having n+1 bits; second counter means for providing a second signal having n+1 bits; multiplexer means for receiving both said first signal and said second signal and selecting either said first or second signal as its output; first comparator means for comparing the most significant bit of said first signal with the most significant bit of said signal and producing a first control signal indicative of said comparison; second comparator means for comparing the n least significant bits of said first signal with the n least significant bits of said second signal, and producing a second control signal indicative of said comparison; and logic means, responsive to said first control signal and said control signal, for producing both a first indicator signal indicative of said memory circuit being empty or not empty and a second indicator signal indicative of said memory circuit being full or not full.

Claim 7

A control circuit for a FIFO (first in first out) memory circuit for providing address information to a FIFO memory means having an address field of n bits, said control circuit comprising: first counter means for providing a first signal having n+1 bits; second counter means for providing a second signal having n+1 bits; multiplexer means for receiving both said first signal and said second signal and selecting either said first or second signal as its output; first comparator means for comparing the most significant bit of said first signal with the most significant bit of said signal and producing a first control signal indicative of said comparison; second comparator means for comparing the n least significant bits of said first signal with the n least significant bits of said second signal, and producing a second control signal indicative of said comparison; and logic means, responsive to said first control signal and said control signal, for producing both a first indicator signal indicative of said memory circuit being empty or not empty and a second indicator signal indicative of said memory circuit being full or not full.

Claim 8

The control circuit of claim 5 wherein said logic means comprises an inverter means and first and second AND gate means, wherein: said first AND gate has one input responsive to said first control signal, a second input responsive to said second control signal, and an output which is said first indicator signal; said inverter having an input responsive to said first control signal and an output which is said first control signal inverted; and, said second AND gate having one input responsive to said inverter first control signal, a second input responsive to said second control signal, and an output which is said second indicator signal.