Bus oriented LIFO/FIFO memory

Claim 2

A memory circuit including a plurality of memory cells all connected to a common input bus and a common output bus and each memory cell including data storage means and a control circuit, said control circuit comprising means for generating a data occupancy status signal, write control means responsive to data occupancy status signals from said memory cell and a selectable adjacent memory cell for controlling the writing of data from said input bus into said data storage means, and read control means responsive to data occupancy status signals from said memory cell and a selectable adjacent memory cell for controlling the reading of data from said data storage means to said output bus.

Claim 3

The control circuit of claim 1 wherein said write control means and said read control means are responsive to an occupancy status signal from the same adjacent memory cell.

Claim 4

The control circuit of claim 1 wherein said write control means and said read control means are responsive to an occupancy status of signal from different adjacent memory cells.

Claim 5

The control circuit of claim 1 wherein said write control means writes data into said data storage means in response to a group of signals selectable from a set comprising a first group including a first control signal and the occupancy status signals from said memory cell and a first adjacent memory cell and a second group including a second control signal and the occupancy status signals from said memory cell and a second adjacent memory cell.

Claim 6

The control circuit of claim 1 wherein said read control means reads data from said data storage means in response to a group of signals selectable from a set comprising a first group including a first control signal and the occupancy status signals from said memory cell and a first adjacent memory cell and a second group including a second control signal and the occupancy status signals from said memory cell and a second adjacent memory cell.

Claim 7

The control circuit of claim 1 wherein said write control means sets said data occupancy status signal generating means to an occupied status before the writing of data into said data storage means, and said read control means clears said data occupancy status signal generating means after the reading of data from said data storage means.

Claim 8

The control circuit of claim 1 further including means responsive to a first state of a binary control signal for gating the same adjacent occupancy status signal to said read control means and said write control means and responsive to a second state of said binary control signal for gating different adjacent cell occupancy status signals to said read control means and said write control means.

Claim 9

The control circuit of claim 7 wherein said gating means includes means responsive to a second control signal for changing the adjacent occupancy status signal gated to both said read control means and said write control means.

Claim 10

A memory circuit comprising an initialization circuit and a first, a last, and at least one intermediate memory cell all connected to a common input bus and a common output bus, each memory cell including a data storage means for storing from said input bus and outputting data to said output bus and a control circuit including a data occupancy status signal means and a write control means wherein said write control means of said first memory cell is responsive to a data occupancy status signal from said first memory cell and a signal selected from a group of signals including a first output signal from said initialization circuit and a data occupancy signal from a subsequent adjacent memory cell for controlling the writing of data into the associated data storage means, said write control means of said at least one intermediate memory cell is responsive to a data occupancy status signal from said at least one intermediate memory cell and a data occupancy status signal from a selected adjacent memory cell for controlling the writing of data into the associated data storage means, said write control means of said last memory cell is responsive to said data occupancy signal from said last memory cell and a signal selected from a group of signals including a data occupancy status signal from a preceding adjacent memory cell and a second output signal from said initialization circuit for controlling the writing of data into the associated data storage means, and said initialization circuit generating said first output signal to said first memory cell in response to said data occupancy status signal from said last memory cell and an all memory cells empty signal and generating said second output signal to said last memory cell in response to said data occupancy status signal from said first memory cell and said all memory cells empty signal.

Claim 11

A memory circuit comprising an initialization circuit and a first, a last, and at least one intermediate memory cell all connected to a common input bus and a common output bus, each memory cell including a data storage means for storing from said input bus and outputting data to said output bus and a control circuit including a data occupancy status signal means and a write control means wherein said write control means of said first memory cell is responsive to a data occupancy status signal from said first memory cell and a signal selected from a group of signals including a first output signal from said initialization circuit and a data occupancy signal from a subsequent adjacent memory cell for controlling the writing of data into the associated data storage means, said write control means of said at least one intermediate memory cell is responsive to a data occupancy status signal from said at least one intermediate memory cell and a data occupancy status signal from a selected adjacent memory cell for controlling the writing of data into the associated data storage means, said write control means of said last memory cell is responsive to said data occupancy signal from said last memory cell and a signal selected from a group of signals including a data occupancy status signal from a preceding adjacent memory cell and a second output signal from said initialization circuit for controlling the writing of data into the associated data storage means, and said initialization circuit generating said first output signal to said first memory cell in response to said data occupancy status signal from said last memory cell and an all memory cells empty signal and generating said second output signal to said last memory cell in response to said data occupancy status signal from said first memory cell and said all memory cells empty signal.

Claim 12

The memory circuit of claim 9 wherein each control circuit includes a read control means wherein said read control means of said first memory cell is responsive to said data occupancy status signal from said first memory cell and the signal selected from a group of signals including said first output signal from said initialization circuit and said data occupancy from said subsequent adjacent memory cell for controlling the reading of data into the associated data storage means, said read control means of said at least one intermediate memory cell is responsive to said data occupancy status signal from said at least one intermediate memory cell and said data occupancy status signal of said selected adjacent memory cell for controlling the reading of data into the associated data storage means, and said read control means of said last memory cell is responsive to said data occupancy signal from said last memory cell and the signal selected from a group of signals including said data occupancy status signal from said preceding adjacent intermediate memory cell and said second output signal from said initialization circuit for controlling the reading of data with the associated data storage means.