FIFO arrangement for temporary data storage

Claim 2

A FIFO arrangement for temporary data storage which includes: a random access memory having an input and an output, a control system for said random access memory, a first and a second output buffer register connected in series relation to the output of said random access memory, a single input buffer register connected to the input of said random access memory, wherein said control system includes: a first control logic for controlling operation of said input buffer register, having: first means for storing write requests one at a time, second means for storing the condition of said input buffer register, said second means being operatively associated with additional means arranged for setting said second storing means in response to the presence of an external writing request stored in said first storing means when said second storing means are in a condition indicating that said input buffer register is empty, generating means for generating an internal writing request signal and directing it to said randon access memory when said second storing means indicate that said input buffer register is loaded and as long as said random access memory has not acknowledged said internal writing request, said generating means being arranged and connected to reset said second storing means into a condition indicating that said input buffer register is empty when said writing request has been acknowledged, a second control logic having: third storing means for storing the condition of said first output buffer register, fourth storing means for storing the condition of said second buffer register, supplemental means for generating an internal reading request and directing it to said random access memory when said third storing means are in a condition indicating that the first output buffer register is empty and as long as said reading request has not been acknowledged, and for resetting said thid storing means into a condition indicating that said first output register is loaded as soon as the reading request has been acknowledged, a unit for setting said fourth storing means when the third storing means indicate that the first output register is loaded and said fourth storing means indicate that the second output register is empty, said unit being connected to simultaneously reset said third storing means into a condition indicating that said first output buffer register is empty, and means for setting said fourth storing means when the latter indicates said second output buffer register is loaded and after an external signal representative of a request for reading out of the said second output buffer register has been delivered, and a logic circuit for solving conflicts between an internal writing-in request and an internal reading-out request.

Claim 3

A FIFO arrangement according to claim 1, wherein said additional means for setting said second storing means in response to the presence of an external writing request are arranged for setting the first storing means whereby the latter then indicates there is no external writing request which is stored.

Claim 4

An arrangement according to claim 1, wherein said generating means for generating an internal writing request is arranged for also delivering said writing request signal responsive to said first storing means being in a condition indicating that an external writing request is stored.

Claim 5

An arrangement according to claim 1, wherein said supplemental means for generating an internal reading request and directing it to said random access memory is arranged to also deliver a reading request responsive to said fourth storing means being in a condition indicating said said second output buffer register is empty.

Claim 6

A FIFO arrangement for temporary data storage which includes: a random access memory having an input and an output, a control system for said random access memory, a first and second output buffer registers connected in series relating to the output of said random access memory, a single input buffer register connected to the input of said random access memory, wherein said control system includes: a first control logic for controlling operation of said input buffer register, having: first means for storing write requests one at a time, second means for storing the condition of said input buffer register, said second means being operatively associated with additional means arranged for setting said second storing means in response to the presence of an external writing request stored in said first storing means when said second storing means are in a condition indicating that said input buffer register is empty, generating means for generating an internal writing request signal and directing it to said random access memory responsive to simultaneous receipt of a first enabling signal and a signal from said second storing means indicating that said input buffer register is loaded and as long as said random access memory has not acknowledged said internal writing request, said generating means being arranged and connected to reset said second storing means into a condition indicating said said input buffer register is empty when said writing request has been acknowledged, a second control logic having: third storing means for storing the condition of said first output buffer register, fourth storing means for storing the condition of said second buffer register, supplemental means for generating an internal reading request and directing it to said random access memory responsive to simultaneous receipt of a second enabling signal and a signal from said third storing means indicating that the first output buffer register is empty and as long as said reading request has not been acknowledged, and for resetting said third storing means into a condition indicating that said first output register is loaded as soon as the reading request has been acknowledged, a unit for setting said fourth storing means when the third storing means indicate that the first output register is loaded and said fourth storing means indicate that the second output register is empty, said unit being connected to simultaneously reset said third storing means into a condition indicating said said first output buffer register is empty, and means for setting said fourth storing means when the latter indicates said second output buffer register is loaded and after an internal signal representative of a request for reading out of the said second output buffer register has been delivered, and a logic circuit for solving conflicts between an internal writing-in request and an internal reading-out request and delivering one only of said first and second enabling signals at a time.

Claim 7

A FIFO arrangement for temporary data storage which includes: a random access memory having an input and an output, a control system for said random access memory, a first and second output buffer registers connected in series relating to the output of said random access memory, a single input buffer register connected to the input of said random access memory, wherein said control system includes: a first control logic for controlling operation of said input buffer register, having: first means for storing write requests one at a time, second means for storing the condition of said input buffer register, said second means being operatively associated with additional means arranged for setting said second storing means in response to the presence of an external writing request stored in said first storing means when said second storing means are in a condition indicating that said input buffer register is empty, generating means for generating an internal writing request signal and directing it to said random access memory responsive to simultaneous receipt of a first enabling signal and a signal from said second storing means indicating that said input buffer register is loaded and as long as said random access memory has not acknowledged said internal writing request, said generating means being arranged and connected to reset said second storing means into a condition indicating said said input buffer register is empty when said writing request has been acknowledged, a second control logic having: third storing means for storing the condition of said first output buffer register, fourth storing means for storing the condition of said second buffer register, supplemental means for generating an internal reading request and directing it to said random access memory responsive to simultaneous receipt of a second enabling signal and a signal from said third storing means indicating that the first output buffer register is empty and as long as said reading request has not been acknowledged, and for resetting said third storing means into a condition indicating that said first output register is loaded as soon as the reading request has been acknowledged, a unit for setting said fourth storing means when the third storing means indicate that the first output register is loaded and said fourth storing means indicate that the second output register is empty, said unit being connected to simultaneously reset said third storing means into a condition indicating said said first output buffer register is empty, and means for setting said fourth storing means when the latter indicates said second output buffer register is loaded and after an internal signal representative of a request for reading out of the said second output buffer register has been delivered, and a logic circuit for solving conflicts between an internal writing-in request and an internal reading-out request and delivering one only of said first and second enabling signals at a time.

Claim 8

An arrangement according to claim 5, wherein said logic circuit comprises: a first latch connected to deliver said first enabling signal when in set condition,

Claim 9

a second latch connected to deliver said second enabling signal when in set condition, and a mutual exclusion logic for preventing simultaneous setting of said two latches, having first inhibiting gate means for controlling transmission of an internal writing request to said first latch as a set signal thereof, second inhibiting gate means for controlling transmission of an internal reading request to said second latch as a set signal thereof, and a priority circuit for continuously applying complementary binary signal to said inhibiting gate means for causing one only of said inhibiting gate means to stop transmission upon simultaneous application of requests to both said inhibiting gate means.

Claim 10

a second latch connected to deliver said second enabling signal when in set condition, and a mutual exclusion logic for preventing simultaneous setting of said two latches, having first inhibiting gate means for controlling transmission of an internal writing request to said first latch as a set signal thereof, second inhibiting gate means for controlling transmission of an internal reading request to said second latch as a set signal thereof, and a priority circuit for continuously applying complementary binary signal to said inhibiting gate means for causing one only of said inhibiting gate means to stop transmission upon simultaneous application of requests to both said inhibiting gate means.