Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
259 words
A random access memory arrangement comprising: a random access memory (10, 11) having common read and write data terminals; means (12) for supplying input data to said read and write data terminals for writing in said random access memory (10, 11); a first output latch circuit (13) connected to said read and write data terminals; a second output latch circuit (14) connected to said first output latch circuit; and means for supplying control signals: to enable said random access memory (10, 11) to write said input data therein at given addresses in synchronism with write pulses of a write pulse signal; to enable said random access memory (10, 11) to read output data from given addresses therein in synchronism with read pulses of a read pulse signal, said read pulse signal being asynchronous with said write pulse signal; to control said first output latch circuit (13) to hold and to supply to said second output latch circuit (14) data supplied to said first output latch circuit (13) immediately prior to each said write pulse, and to pass therethrough to said second output latch circuit (14) data supplied to said first output latch circuit (13) at all other times; and to control said second output latch circuit (14) to hold the data supplied to said second output latch circuit _(14) by said first output latch circuit (13) immediately prior to the beginning of each said read pulse until the beginning of the next succeeding said read pulse and to supply the data so held to an output of said arrangement.
Claim 2
Dependent Claim
259 words
A random access memory arrangement comprising: a random access memory (10, 11) having common read and write data terminals; means (12) for supplying input data to said read and write data terminals for writing in said random access memory (10, 11); a first output latch circuit (13) connected to said read and write data terminals; a second output latch circuit (14) connected to said first output latch circuit; and means for supplying control signals: to enable said random access memory (10, 11) to write said input data therein at given addresses in synchronism with write pulses of a write pulse signal; to enable said random access memory (10, 11) to read output data from given addresses therein in synchronism with read pulses of a read pulse signal, said read pulse signal being asynchronous with said write pulse signal; to control said first output latch circuit (13) to hold and to supply to said second output latch circuit (14) data supplied to said first output latch circuit (13) immediately prior to each said write pulse, and to pass therethrough to said second output latch circuit (14) data supplied to said first output latch circuit (13) at all other times; and to control said second output latch circuit (14) to hold the data supplied to said second output latch circuit _(14) by said first output latch circuit (13) immediately prior to the beginning of each said read pulse until the beginning of the next succeeding said read pulse and to supply the data so held to an output of said arrangement.
Claim 3
Dependent Claim
57 words
An arrangement according to claim 1 wherein said means for supplying input data comprises an input latch circuit (12) connected to said read and write data terminals of said random access memory (10, 11), said input latch circuit (12) supplying said input data to said read and write data terminals under control of said write pulse signal.
Claim 4
Dependent Claim
45 words
An arrangement according to claim 2 wherein said means for supplying control signals comprises means (22) to derive a read inhibit pulse signal in synchronism with said write pulse signal, said read inhibit pulse signal being supplied to control said first output latch circuit (13).
Claim 5
Dependent Claim
58 words
An arrangement according to claim 1, claim 2 or claim 3 further comprising a write address generator (17) for supplying write addresses to said random access memory (10, 11) by way of a write address latch circuit (15), said write address generator (17) and said write address latch circuit (15) being synchronously controlled by said write pulse signal.
Claim 6
Dependent Claim
53 words
An arrangement according to claim 4 further comprising a read address generator (19) for supplying read addresses to said random access memory (10, 11) by way of a read address latch circuit (16), said read address generator (19) and said read address latch circuit (16) being synchronously controlled by said read pulse signal.
Claim 7
Dependent Claim
32 words
An arrangement according to any one of the preceding claims wherein said first output latch circuit (13) is a transparent latch circuit controlled by a signal derived from said write pulse signal.
Claim 8
Dependent Claim
29 words
An arrangement according to any one of the preceding claims wherein said second output latch circuit (14) is an edge-triggered latch circuit (14) controlled by said read pulse signal.