US4119946A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Comparison apparatus, e.g. for use in character recognition
Assignee: National Research Development Corp UK
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Filing: 1977-05-20
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Granted: 1978-10-10
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Expires: 1997-05-20
Abstract
Abstract A succession of signals forming the components of an input vector are compared simultaneously with a plurality of reference vectors as the components of the reference vectors are read out in time parallel fashion from a plurality of registers. The comparisons are effected component by component by a plurality of comparators, one per reference vector. The outputs of the comparators are applied to respective integrators or accumulators. At the completion of the comparisons, that integrator or accumulator which stores an extreme value in a predetermined sense indicates the reference vector with which the input vector matches most closely. The vectors may represent characters or samples of waveforms such as speech waveforms, for example, and the invention may be applied to optical character recognition, speed recognition and so on. The apparatus can be implemented from standard, off-the-shelf solid state circuits and avoids the need for purpose built circuitry, such as fusible resistor matrix read-only memories and, therefore, avoids the additional expense and lack of flexibility of such circuitry.
Inventors
- 👤 Wilfred Kenelm Taylor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:00
CPC Classifications
G; G10; G10L; G10L15/00; G06; G06F; G06F7/00; G06F7/02; G06V; G06V10/00; G06V10/70; G06V10/74; G06V10/75; G06V10/751
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
249 words
Apparatus for comparing vectors, comprising means defining a plurality of n.M shift registers for storing a plurality M of reference vectors each having N components represented by corresponding groups of n bits, where N and M are integers greater than 1, and n is selected from the group of small integers including unity, each shift register having a single bit output, means additional to said n.M shift registers for supplying an input vector also having N components represented by corresponding groups of n bits, M comparison devices each adapted to compare n bits of said input vector with n bits of its corresponding one of said M reference vectors and to provide a comparison signal representing the results of the comparison, means operative in a succession of comparison operations to present the bits of the input vector n at a time, simultaneously to the respective comparison devices of all M said reference vectors and concurrently to present the corresponding bits of the reference vectors from the single bit outputs of said registers to the respective comparison devices, and a plurality M of summating devices operative to accumulate output signals in response to the comparison signals from the M comparison devices respectively and to provide such output signals at the conclusion of the comparison operations, that output signal whose value is at one extreme of the range of values of the output signals denoting the one of the M reference vectors with which the input vector makes the closest match.
Claim 2
Dependent Claim
249 words
Apparatus for comparing vectors, comprising means defining a plurality of n.M shift registers for storing a plurality M of reference vectors each having N components represented by corresponding groups of n bits, where N and M are integers greater than 1, and n is selected from the group of small integers including unity, each shift register having a single bit output, means additional to said n.M shift registers for supplying an input vector also having N components represented by corresponding groups of n bits, M comparison devices each adapted to compare n bits of said input vector with n bits of its corresponding one of said M reference vectors and to provide a comparison signal representing the results of the comparison, means operative in a succession of comparison operations to present the bits of the input vector n at a time, simultaneously to the respective comparison devices of all M said reference vectors and concurrently to present the corresponding bits of the reference vectors from the single bit outputs of said registers to the respective comparison devices, and a plurality M of summating devices operative to accumulate output signals in response to the comparison signals from the M comparison devices respectively and to provide such output signals at the conclusion of the comparison operations, that output signal whose value is at one extreme of the range of values of the output signals denoting the one of the M reference vectors with which the input vector makes the closest match.
Claim 3
Dependent Claim
37 words
Apparatus according to claim 1, wherein the input vector is also held in an input register from which the input vector bits are read out in synchronism with the reading of bits from the reference vector registers.
Claim 4
Dependent Claim
81 words
Apparatus according to claim 1, wherein n is unity, the vectors are binary words, M reference vectors of N-bits each are held in M, N-bit registers and comprising means arranged to read the reference vectors bit by bit out of the registers under control of clock pulses in synchronism with the presentation to the comparison devices of the bits of the input vector, the comparison devices being arranged to compare the input vector bits with the reference vector bits in parallel.
Claim 5
Dependent Claim
14 words
Apparatus according to claim 3, wherein each comparison device is an exclusive OR gate.
Claim 6
Dependent Claim
13 words
Apparatus according to claim 4, wherein each summating device is an analog integrator.
Claim 7
Dependent Claim
132 words
Apparatus according to claim 5, including M match comparators driven by said output signals of respective ones of said M summating devices for triggering of the one of said match comparators whose reference vector best matches the input vector, and further including means for ranking pattern similarity from best match down to a selected level of match and comprising M flip-flops each having an input connected to the output of the corresponding one of said M match comparators, M switches each responsive to the output of the corresponding one of said M flip-flops for applying such output to the corresponding one of said M summating devices, switch means actuable for resetting said M summating devices, and control register means synchronized with said M referrence vector registers for actuating said reset switch means.
Claim 8
Dependent Claim
85 words
Apparatus according to claim 1, wherein the vectors are words having n-bit bytes where n is greater than 1, groups of n registers store the components of the vectors in byte-serial, bit-parallel form, and comprising means arranged to read the reference vectors byte by byte out of the registers under control of clock pulses in synchronism with the presentation to the comparison devices of bytes of the input vector, the comparison devices being arranged to compare the input vector bytes with the reference vector bytes.
Claim 9
Dependent Claim
37 words
Apparatus according to claim 7, wherein each comparison device comprises n exclusive OR gates to which are applied respective bits of each input vector byte and respective bits of each reference vector byte from the corresponding register.
Claim 10
Dependent Claim
30 words
Apparatus according to claim 8, wherein each summating device comprises an analog integrator having a summing input connected to outputs of all exclusive OR gates of the corresponding comparison devices.
Claim 11
Dependent Claim
43 words
Apparatus according to claim 1, comprising a source of vectors operative to provide a succession of sets of parallel vector components, and a multiplexer arranged to multiplex the components in serial form and to enter the serialized components in one of said registers.
Claim 12
Dependent Claim
25 words
Apparatus according to claim 10, comprising switching means adapted to connect the output of the multiplexer to any selected one of the reference vector registers.
Claim 13
Dependent Claim
80 words
Apparatus according to claim 11, including an analog-to-digital converter defining said vector source, a NAND gate, a latch flip-flop set by the onset of an input to said converter, a clock operable through said NAND gate for controlling said converter and multiplexer and registers, a counter responsive to a number of clock pulses corresponding to the number of stages of said selected register for resetting said latch flip-flop, said latch flip-flop being connected to disable said NAND gate when reset.
Claim 14
Dependent Claim
76 words
Apparatus according to claim 1, wherein the input vector is also held in an input register from which the input vector components are read out in synchronism with the reading of components from the reference vector registers, and comprising a source of a vector operative to provide a succession of sets of parallel vector components, and a multiplexer arranged to multiplex the components in serial form and to enter the serialized components in the input register.
Claim 15
Dependent Claim
25 words
Apparatus according to claim 1, comprising a plurality of sensors arranged to scan characters to be recognized to provide the components of the input vector.
Claim 16
Dependent Claim
44 words
Apparatus according to claim 1, comprising means for periodically sampling a waveform to provide a succession of analog samples and an analog to digital converter arranged to convert each sample to a digital value consisting of a plurality of the components of a vector.
Claim 17
Dependent Claim
12 words
Apparatus according to claim 1, in which n is less than N.
References Cited (Backward Citations)
US3187305A
Cited
US3576534A
Cited
US3905018A
Cited
US3849762A
Cited
US3878509A
Cited
US4014000A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-09 | 1982-04-10 | 1982-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-09 | 1986-04-10 | 1986-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-09 | 1990-04-10 | 1990-10-10 | $7700.00 | Window Closed / Lapsed |