US3849762A
Expired / Lapsed
US
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Digital information processing apparatus for pattern recognition
Assignee: Hitachi Ltd
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Filing: 1973-03-07
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Granted: 1974-11-19
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Expires: 1993-03-07
Abstract
Abstract A digital information processing apparatus for pattern recognition comprising a memory unit for storing information consisting of a plurality of words representing an unknown character and a plurality of pieces of information representing a plurality of standard characters each of which consists of the same number of words as the information representing the unknown character and which are stored in series so that the words of the corresponding orders in the respective information are sequentially stored, means for reading out of the memory unit the information representing the unknown character every each word and each piece of information representing one of the standard characters every each word, means for comparing these information thus read by means of each bit of the word and detecting the number in which the compared bits agree with each other, and means for adding a correlation constant predetermined in accordance with the standard character under the comparison by the number of agreements, so that similarity of the unknown character with each standard character is determined by means of a single instruction.
Inventors
- 👤 Y Fujimoto
- 👤 T Hananoi
- 👤 M Yasuda
- 👤 M Ota
- 👤 H Kokido
- 👤 H Makihara
- 👤 M Kuramizu
- 👤 S Kadota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:00
CPC Classifications
G; G06; G06V; G06V10/00; G06V10/70; G06V10/74; G06V10/75
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
334 words
A digital information processing apparatus for pattern recognition comprising: a memory unit for storing a piece of information representing an unknown pattern and M pieces of information representing M standard patterns (M being a given integral number) in a predetermined sequence of addresses word by word, each piece of information including N words (N being a given integral number); memory address register means for designating in said predetermined sequence the N (M + 1) addresses of said memory unit at which said M + 1 pieces of information are stored so that each piece of information of said unknown pattern and said M standard patterns is read out of said memory unit word by word in said predetermined sequence; data register means for temporarily storing each piece of information read out of said memory unit word by word; first register means for storing only said information of said unknown pattern selectively transferred from said data register means; second register means for stoRing only said plurality of pieces of information of said standard patterns selectively and sequentially transferred from said data register means; M correlation constant registers each storing a predetermined correlation constant corresponding to each of said M standard patterns; M correlation detectors each comparing said information of said unknown pattern stored in said first register means with said information of one of said standard patterns stored in said second register means by means of each bit and detecting the number of times of agreement between said unknown pattern and said standard pattern; and M adders provided for the respective one of said M standard patterns each for adding said correlation constant stored in a corresponding one of said correlation contant registers by the number of times of the agreement between said unknown pattern and said standard pattern in response to an output from said correlation detector, whereby the similarity between said unknown pattern and each of said M standard patterns is determined on the basis of the content of each of said adders.
Claim 2
Dependent Claim
334 words
A digital information processing apparatus for pattern recognition comprising: a memory unit for storing a piece of information representing an unknown pattern and M pieces of information representing M standard patterns (M being a given integral number) in a predetermined sequence of addresses word by word, each piece of information including N words (N being a given integral number); memory address register means for designating in said predetermined sequence the N (M + 1) addresses of said memory unit at which said M + 1 pieces of information are stored so that each piece of information of said unknown pattern and said M standard patterns is read out of said memory unit word by word in said predetermined sequence; data register means for temporarily storing each piece of information read out of said memory unit word by word; first register means for storing only said information of said unknown pattern selectively transferred from said data register means; second register means for stoRing only said plurality of pieces of information of said standard patterns selectively and sequentially transferred from said data register means; M correlation constant registers each storing a predetermined correlation constant corresponding to each of said M standard patterns; M correlation detectors each comparing said information of said unknown pattern stored in said first register means with said information of one of said standard patterns stored in said second register means by means of each bit and detecting the number of times of agreement between said unknown pattern and said standard pattern; and M adders provided for the respective one of said M standard patterns each for adding said correlation constant stored in a corresponding one of said correlation contant registers by the number of times of the agreement between said unknown pattern and said standard pattern in response to an output from said correlation detector, whereby the similarity between said unknown pattern and each of said M standard patterns is determined on the basis of the content of each of said adders.
Claim 3
Dependent Claim
56 words
A digital information processing apparatus according to claim 1, in which said information of said unknown pattern is stored so that the first to the N-th words are sequentially stored, and said information of said standard patterns is stored in series so that the words of the corresponding orders in the respective information are sequentially stored.
Claim 4
Dependent Claim
42 words
A digital information processing apparatus according to claim 2, further comprising control means for reading from said memory unit and transferring to said data register a word of information on each of said unknown pattern and said standard patterns in one cycle.
Claim 5
Dependent Claim
77 words
A digital information processing apparatus according to claim 3, further comprising control means for detecting through said correlation detector the agreement for each bit between the L-th word (L being smaller than N) of the information of said unknown pattern and the L-th word of the H-th standard pattern (H being smaller than M) and storing the information of the L-th word of the (H + 1)th standard pattern in said second register means, in one cycle.
Claim 6
Dependent Claim
126 words
A digital information processing apparatus according to claim 3, in which said control means comprises a shift register including M + 1 flip-flops, one of said flip-flops being set in the state of 1, the others of said flip-flops being set in the state of 0, means for applying one shift pulse to said shift register in one cycle, gate means for controlling the application of the data from said data register means to said first register means in response to the output from one of said flip-flops of said shift register, and another gate means for controlling the application of the data from said data register means to said second register means in response to the output from the other flip-flops of said shift register.
Claim 7
Dependent Claim
117 words
A digital information processing apparatus according to claim 2, further comprising a control means including: a down counter the content of which is initially set at N and reduced by one each time a word of the information of said unknown pattern or said M standard patterns is read out of said memory unit, a flip-flop which is reset in response to a signal produced from said down counter when the content of said counter is reduced to zero, and means for stopping the operation of the correlation detector in response to an output from said flip-flop, said correlation detector comparing the information stored in said first register means and that stored in said second register means.
References Cited (Backward Citations)
US3295103A
Cited
US3492646A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-11-18 | 1978-05-20 | 1978-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-11-18 | 1982-05-20 | 1982-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-11-18 | 1986-05-20 | 1986-11-19 | $7700.00 | Window Closed / Lapsed |