US6437650B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-locked loop or delay-locked loop circuitry for programmable logic devices
Assignee: Altera Corp
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Filing: 2001-05-15
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Granted: 2002-08-20
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Expires: 2021-05-15
Abstract
Abstract A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
Inventors
- 👤 Chiakang Sung
- 👤 Joseph Huang
- 👤 Bonnie I. Wang
- 👤 Robert R. N. Bielby
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:20
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L7/0818; H03L7/099; H03L7/0995; H03L7/0996; H03L7/0997
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
130 words
A programmable logic device comprising: PLL/DLL circuitry adapted to receive an input clock signal and to produce modified and pilot clock signals which are variably shifted in phase relative to the input clock signal; a clock signal distribution network adapted to convey the modified clock signal to a location that is approximately central to the programmable logic device and from that location to distribute the modified clock signal to circuitry on the programmable logic device that makes use of the modified clock signal; and feedback loop circuitry adapted to substantially parallel and duplicate a portion of the clock signal distribution network and to convey the pilot signal back to the PLL/DLL circuitry for use in determining a phase shift of the modified clock signal relative to the input clock signal.
Claim 2
Dependent Claim
130 words
A programmable logic device comprising: PLL/DLL circuitry adapted to receive an input clock signal and to produce modified and pilot clock signals which are variably shifted in phase relative to the input clock signal; a clock signal distribution network adapted to convey the modified clock signal to a location that is approximately central to the programmable logic device and from that location to distribute the modified clock signal to circuitry on the programmable logic device that makes use of the modified clock signal; and feedback loop circuitry adapted to substantially parallel and duplicate a portion of the clock signal distribution network and to convey the pilot signal back to the PLL/DLL circuitry for use in determining a phase shift of the modified clock signal relative to the input clock signal.
Claim 3
Dependent Claim
35 words
The device defined in claim 1 wherein the PLL/DLL circuitry comprises: programmable circuitry adapted to programmably select for the pilot signal any one of a plurality of different phase relationships to the modified clock signal.
Claim 4
Dependent Claim
31 words
The device defined in claim 1 further comprising: programmable circuitry adapted to programmably apply the input clock signal to the clock signal distribution network in lieu of the modified clock signal.
Claim 5
Dependent Claim
30 words
The device defined in claim 1 wherein the circuitry on the programmable logic device that makes use of the modified clock signal comprises a plurality of regions of programmable logic.
Claim 6
Dependent Claim
29 words
The device defined in claim 1 wherein the circuitry on the programmable logic device that makes use of the modified clock signal comprises a plurality of I/O register regions.
Claim 7
Dependent Claim
33 words
The device defined in claim 1 further comprising: a clock signal output terminal connected to the feedback loop circuitry and adapted to output the pilot clock signal to circuitry external to the device.
Claim 8
Dependent Claim
34 words
The device defined in claim 6 wherein the circuitry on the programmable logic device that makes use of the modified clock signal comprises I/O register circuitry disposed adjacent to the clock signal output terminal.
Claim 9
Dependent Claim
90 words
The device defined in claim 1 wherein the PLL/DLL circuitry is PLL circuitry comprising: phase/frequency detector circuitry adapted to produce output signals indicative of a phase difference between the input clock signal and the pilot clock signal from the feedback loop circuitry; charge pump circuitry adapted to respond to the output signals of the phase/frequency detector circuitry by producing an output voltage indicative of the phase difference; and voltage controlled oscillator circuitry adapted to produce the modified clock signal with a frequency which is a function of the output voltage.
Claim 10
Dependent Claim
97 words
The device defined in claim 1 wherein the PLL/DLL circuitry is DLL circuitry comprising: phase/frequency detector circuitry adapted to produce output signals indicative of a phase difference between the input clock signal and the pilot clock signal from the feedback loop circuitry; charge pump circuitry adapted to respond to the output signals of the phase/frequency detector circuitry by producing an output voltage indicative of the phase difference; and voltage controlled delay line circuitry adapted to produce the modified clock signal by delaying the input clock signal by an amount which is a function of the output voltage.
Claim 11
Dependent Claim
32 words
A digital processing system comprising: processing circuitry; a memory coupled to said processing circuitry; and a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.
Claim 12
Dependent Claim
18 words
A printed circuit board on which is mounted a programmable logic device as defined in claim 1 .
Claim 13
Dependent Claim
25 words
The printed circuit board defined in claim 11 further comprising: a memory mounted on the printed circuit board and coupled to the programmable logic device.
Claim 14
Dependent Claim
25 words
The printed circuit board defined in claim 11 further comprising: processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.
Claim 15
Independent Claim
63 words
A method of operating a programmable logic device comprising: passing clock and pilot clock signals through respective first and second clock signal distribution circuitries on the device, the second circuitry substantially paralleling and duplicating a representative portion of the first circuitry; and using the pilot clock signal, after it has passed through the second circuitry, in selecting a phase for the clock signal.
Claim 16
Independent Claim
63 words
A method of operating a programmable logic device comprising: passing clock and pilot clock signals through respective first and second clock signal distribution circuitries on the device, the second circuitry substantially paralleling and duplicating a representative portion of the first circuitry; and using the pilot clock signal, after it has passed through the second circuitry, in selecting a phase for the clock signal.
Claim 17
Dependent Claim
59 words
The method defined in claim 14 wherein the using comprises: comparing a phase and frequency of an input clock signal to a phase and frequency of the pilot clock signal after it has passed through the second circuitry in order to produce an error signal for use in controlling PLL/DLL circuitry that produces the clock and pilot clock signals.
Claim 18
Dependent Claim
22 words
The method defined in claim 14 further comprising: selecting the pilot clock signal as a possibly phase-shifted version of the clock signal.
Claim 19
Dependent Claim
35 words
The method defined in claim 14 further comprising: producing a plurality of differently phase-shifted versions of the clock signal; and selecting the pilot clock signal from among the differently phase-shifted versions of the clock signal.
Claim 20
Dependent Claim
62 words
A programmable logic device comprising: first and second clock signal distribution circuitries respectively adapted to convey clock and pilot clock signals, the second circuitry substantially paralleling and duplicating a representative portion of the first circuitry; and PLL/DLL circuitry responsive to the pilot clock signal, after it has passed through the second circuitry, in order to select a phase for the clock signal.
Claim 21
Dependent Claim
62 words
A programmable logic device comprising: first and second clock signal distribution circuitries respectively adapted to convey clock and pilot clock signals, the second circuitry substantially paralleling and duplicating a representative portion of the first circuitry; and PLL/DLL circuitry responsive to the pilot clock signal, after it has passed through the second circuitry, in order to select a phase for the clock signal.
Claim 22
Dependent Claim
43 words
The device defined in claim 18 wherein the PLL/DLL circuitry produces a plurality of differently phase-shifted versions of the clock signal, and wherein the device further comprises: selection circuitry adapted to select any one of the differently phase-shifted versions of the clock signal.
Claim 23
Dependent Claim
12 words
The device defined in claim 19 wherein the selection circuitry is programmable.
Claim 24
Dependent Claim
56 words
The device defined in claim 18 wherein the PLL/DLL circuitry comprises: phase/frequency detector circuitry adapted to compare a phase and frequency of an input clock signal to a phase and frequency of the pilot clock signal after it has passed through the second circuitry to produce an error signal for use in controlling the PLL/DLL circuitry.
Claim 25
Dependent Claim
32 words
The device defined in claim 21 further comprising: programmable circuitry adapted to apply the input clock signal to the first circuitry in lieu of a clock signal produced by the PLL/DLL circuitry.
Claim 26
Dependent Claim
87 words
The device defined in claim 18 wherein the first circuitry is adapted to convey the clock signal to a central location on the device and to distribute the clock signal from that location to a plurality of other portions of the device, including a portion that is proximate the PLL/DLL circuitry, and wherein the second circuitry is adapted to convey the pilot clock signal to the central location and from that location to the PLL/DLL circuitry, substantially paralleling and duplicating the first circuitry as it does so.
References Cited (Backward Citations)
US3473160A
Cited
US4494021A
Cited
US4719593A
Cited
US4633488A
Cited
EP0266065A2
Cited
US4847516A
Cited
US5133064A
Cited
JPH01137646A
Cited
US5349544A
Cited
US4959646A
Cited
US4868522A
Cited
US5075575A
Cited
US5072195A
Cited
USRE35797E
Cited
US5204555A
Cited
US5079519A
Cited
US5420544A
Cited
US5397943A
Cited
US5418499A
Cited
US5506878A
Cited
US5815016A
Cited
US5646564A
Cited
US5777360A
Cited
US5742180A
Cited
US5565816A
Cited
US5744991A
Cited
US5699020A
Cited
US5642082A
Cited
US5847617A
Cited
US6215326B1
Cited
US6177844B1
Cited
US6271729B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-19 | 2006-02-18 | 2006-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-19 | 2010-02-18 | 2010-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-19 | 2014-02-18 | 2014-08-20 | $7700.00 | Window Closed / Lapsed |