Phase-locked loop or delay-locked loop circuitry for programmable logic devices

Claim 1

A programmable logic device comprising: a plurality of regions of clock-signal-utilizing circuitry; a clock signal input terminal configured to receive a clock signal from circuitry external to the device; PLL/DLL circuitry configured to receive the clock signal from the clock signal input terminal and to produce a modified clock signal which is shifted in phase relative to the clock signal from the input terminal, the PLL/DLL circuitry being further configured to produce a pilot clock signal which has a predetermined phase relationship to the modified clock signal; clock signal distribution circuitry configured to distribute the modified clock signal to the regions of clock-signal-utilizing circuitry; and feedback loop circuitry configured to substantially parallel and duplicate a portion of the clock signal distribution circuitry and to convey the pilot clock signal from the PLL circuitry through the feedback loop circuitry and back to the PLL/DLL circuitry for use by the PLL/DLL circuitry in a phase comparison with the clock signal from the input terminal in order to determine an amount by which the phase of the modified clock signal is shifted relative to the clock signal from the input terminal.