US6271729B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase-locked loop or delay-locked loop circuitry for programmable logic devices
Assignee: Altera Corp
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Filing: 2000-12-13
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Granted: 2001-08-07
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Expires: 2020-12-13
Abstract
Abstract A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
Inventors
- 👤 Chiakang Sung
- 👤 Joseph Huang
- 👤 Bonnie I. Wang
- 👤 Robert R. N. Bielby
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:37
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L7/0818; H03L7/099; H03L7/0995; H03L7/0996; H03L7/0997
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
108 words
A programmable logic device comprising: PLL/DLL circuitry configured to receive an input clock signal and to produce modified and pilot clock signals which are variably shifted in phase relative to the input clock signal; a clock signal distribution network configured to distribute the modified clock signal to circuitry on the programmable logic device that makes use of the modified clock signal; and feedback loop circuitry configured to substantially parallel and duplicate a portion of the clock signal distribution network and to convey the pilot signal back to the PLL/DLL circuitry for use in determining a phase shift of the modified clock signal relative to the input clock signal.
Claim 2
Dependent Claim
108 words
A programmable logic device comprising: PLL/DLL circuitry configured to receive an input clock signal and to produce modified and pilot clock signals which are variably shifted in phase relative to the input clock signal; a clock signal distribution network configured to distribute the modified clock signal to circuitry on the programmable logic device that makes use of the modified clock signal; and feedback loop circuitry configured to substantially parallel and duplicate a portion of the clock signal distribution network and to convey the pilot signal back to the PLL/DLL circuitry for use in determining a phase shift of the modified clock signal relative to the input clock signal.
Claim 3
Dependent Claim
35 words
The device defined in claim 1 wherein the PLL/DLL circuitry comprises: programmable circuitry configured to programmably select for the pilot signal any one of a plurality of different phase relationships to the modified clock signal.
Claim 4
Dependent Claim
31 words
The device defined in claim 1 further comprising: programmable circuitry configured to programmably apply the input clock signal to the clock signal distribution network in lieu of the modified clock signal.
Claim 5
Dependent Claim
30 words
The device defined in claim 1 wherein the circuitry on the programmable logic device that makes use of the modified clock signal comprises a plurality of regions of programmable logic.
Claim 6
Dependent Claim
29 words
The device defined in claim 1 wherein the circuitry on the programmable logic device that makes use of the modified clock signal comprises a plurality of I/O register regions.
Claim 7
Dependent Claim
33 words
The device defined in claim 1 further comprising: a clock signal output terminal connected to the feedback loop circuitry and configured to output the pilot clock signal to circuitry external to the device.
Claim 8
Dependent Claim
34 words
The device defined in claim 6 wherein the circuitry on the programmable logic device that makes use of the modified clock signal comprises I/O register circuitry disposed adjacent to the clock signal output terminal.
Claim 9
Dependent Claim
90 words
The device defined in claim 1 wherein the PLL/DLL circuitry is PLL circuitry comprising: phase/frequency detector circuitry configured to produce output signals indicative of a phase difference between the input clock signal and the pilot clock signal from the feedback loop circuitry; charge pump circuitry configured to respond to the output signals of the phase/frequency detector circuitry by producing an output voltage indicative of the phase difference; and voltage controlled oscillator circuitry configured to produce the modified clock signal with a frequency which is a function of the output voltage.
Claim 10
Dependent Claim
97 words
The device defined in claim 1 wherein the PLL/DLL circuitry is DLL circuitry comprising: phase/frequency detector circuitry configured to produce output signals indicative of a phase difference between the input clock signal and the pilot clock signal from the feedback loop circuitry; charge pump circuitry configured to respond to the output signals of the phase/frequency detector circuitry by producing an output voltage indicative of the phase difference; and voltage controlled delay line circuitry configured to produce the modified clock signal by delaying the input clock signal by an amount which is a function of the output voltage.
Claim 11
Dependent Claim
32 words
A digital processing system comprising: processing circuitry; a memory coupled to said processing circuitry; and a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.
Claim 12
Dependent Claim
18 words
A printed circuit board on which is mounted a programmable logic device as defined in claim 1 .
Claim 13
Dependent Claim
25 words
The printed circuit board defined in claim 11 further comprising: a memory mounted on the printed circuit board and coupled to the programmable logic device.
Claim 14
Dependent Claim
25 words
The printed circuit board defined in claim 11 further comprising: processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-08-06 | 2005-02-05 | 2005-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-08-06 | 2009-02-05 | 2009-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-08-06 | 2013-02-05 | 2013-08-07 | $7700.00 | Window Closed / Lapsed |