Patent US6420215B1 successfully refreshed from Google Patents.
US6420215B1
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Three-dimensional memory array and method of fabrication
Assignee: SanDisk Technologies LLC
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Filing: 2001-03-21
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Granted: 2002-07-16
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Expires: 2021-03-21
Abstract
Abstract A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally the diode is located in one rail-stack and the other half in the other rail-stack.
Inventors
- 👤 N. Johan Knall
- 👤 Mark Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:27
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/20; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H10D88/01
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
90 words
A method for fabricating a multi-level memory array comprising the steps of: depositing a metal layer; forming at least one layer of silicon on the metal layer where the silicon is doped with a first conductivity type dopant; masking and etching the silicon and metal layers to define a plurality of parallel, spaced-apart rail-stacks; filling the space between the rail-stacks with a dielectric material; planarizing the silicon layer and the dielectric material to form a planarized surface, and forming a layer of material for an antifuse on the planarized surface.
Claim 2
Independent Claim
90 words
A method for fabricating a multi-level memory array comprising the steps of: depositing a metal layer; forming at least one layer of silicon on the metal layer where the silicon is doped with a first conductivity type dopant; masking and etching the silicon and metal layers to define a plurality of parallel, spaced-apart rail-stacks; filling the space between the rail-stacks with a dielectric material; planarizing the silicon layer and the dielectric material to form a planarized surface, and forming a layer of material for an antifuse on the planarized surface.
Claim 3
Dependent Claim
16 words
The method defined by claim 1 , wherein the layer of antifuse material comprises a dielectric.
Claim 4
Dependent Claim
15 words
The method defined by claim 1 wherein the layer of antifuse metal comprises undoped silicon.
Claim 5
Dependent Claim
17 words
The method defined by claim 1 wherein the layer of antifuse material is grown on the rail-stacks.
Claim 6
Dependent Claim
22 words
The method defined by claim 1 wherein the layer of antifuse material is a blanket deposition on the rail-stacks and filling material.
Claim 7
Dependent Claim
31 words
The method defined by claim 2 wherein the silicon layer comprises a first silicon heavily doped with an n-type dopant and a second layer more lightly doped with the n-type dopant.
Claim 8
Dependent Claim
15 words
The method defined by claim 2 wherein the silicon layer is a heavily doped layer.
Claim 9
Dependent Claim
19 words
The method defined by claim 7 wherein the antifuse layer is approximately 80-200 Å thick and comprises silicon dioxide.
Claim 10
Independent Claim
135 words
A method for fabricating a multi-level memory array comprising the steps of: forming a metal layer; forming a first silicon layer heavily doped with a first conductivity type dopant on the metal layer; depositing a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant; forming a layer of an antifuse material on the second silicon layer; depositing a third silicon layer on the layer of antifuse material heavily doped with a second conductivity type dopant; defining spaced-apart rail-stacks from the conductive layer, first and second silicon layers, the layer of antifuse material and third silicon layer; filling space between the rail-stacks with a dielectric, and planarizing the upper surface of the dielectric fill and the third silicon layer.
Claim 11
Independent Claim
135 words
A method for fabricating a multi-level memory array comprising the steps of: forming a metal layer; forming a first silicon layer heavily doped with a first conductivity type dopant on the metal layer; depositing a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant; forming a layer of an antifuse material on the second silicon layer; depositing a third silicon layer on the layer of antifuse material heavily doped with a second conductivity type dopant; defining spaced-apart rail-stacks from the conductive layer, first and second silicon layers, the layer of antifuse material and third silicon layer; filling space between the rail-stacks with a dielectric, and planarizing the upper surface of the dielectric fill and the third silicon layer.
Claim 12
Independent Claim
136 words
A method for fabricating a multi-level memory array comprising the steps of: forming a conductor layer; forming a first silicon layer doped with a first conductivity type dopant on the conductive layer; forming a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant; forming a layer of an antifuse material on the second silicon layer; forming a third silicon layer on the layer of antifuse material doped with a second conductivity type dopant; defining spaced-apart first rail-stacks from the conductive layer, the first and second silicon layers, the layer of antifuse material and the third silicon layer; filling between the first rail-stacks with a dielectric, and planarizing the upper surface of the dielectric fill and the third silicon layer.
Claim 13
Independent Claim
136 words
A method for fabricating a multi-level memory array comprising the steps of: forming a conductor layer; forming a first silicon layer doped with a first conductivity type dopant on the conductive layer; forming a second silicon layer on the first silicon layer, the second silicon layer being more lightly doped than the first layer with the first conductivity type dopant; forming a layer of an antifuse material on the second silicon layer; forming a third silicon layer on the layer of antifuse material doped with a second conductivity type dopant; defining spaced-apart first rail-stacks from the conductive layer, the first and second silicon layers, the layer of antifuse material and the third silicon layer; filling between the first rail-stacks with a dielectric, and planarizing the upper surface of the dielectric fill and the third silicon layer.
Claim 14
Dependent Claim
21 words
The method defined by claim 10 wherein the layer of antifuse material is an oxide grown on the second silicon layer.
Claim 15
Dependent Claim
16 words
The method defined by claim 11 wherein the layer of antifuse material is a deposited dielectric.
Claim 16
Dependent Claim
26 words
The method of claim 10 including repeating the steps of claim 75 to form second rail-stacks disposed above the first rail-stacks perpendicular to the first rail-stacks.
Claim 17
Dependent Claim
24 words
The method defined by claim 13 including additionally etching through the third silicon layer of the first rail-stacks in alignment with the second rail-stacks.
Claim 18
Independent Claim
116 words
A method for fabricating a multi-level memory array comprising the steps of: forming a first silicon layer lightly doped with a first conductivity type dopant; forming a second silicon layer more heavily doped than the first layer with the first conductivity type dopant; depositing a conductive layer on the second silicon layer; depositing a third silicon layer heavily doped with a second conductivity type dopant; etching the first, second and third silicon layers and conductive layers to define a plurality of parallel, spaced-apart rail-stacks; filling the space between the rail-stacks with a dielectric material; planarizing the third silicon layer and the dielectric filling material, and depositing a layer of an antifuse material on the planarized surface.
Claim 19
Independent Claim
116 words
A method for fabricating a multi-level memory array comprising the steps of: forming a first silicon layer lightly doped with a first conductivity type dopant; forming a second silicon layer more heavily doped than the first layer with the first conductivity type dopant; depositing a conductive layer on the second silicon layer; depositing a third silicon layer heavily doped with a second conductivity type dopant; etching the first, second and third silicon layers and conductive layers to define a plurality of parallel, spaced-apart rail-stacks; filling the space between the rail-stacks with a dielectric material; planarizing the third silicon layer and the dielectric filling material, and depositing a layer of an antifuse material on the planarized surface.
Claim 20
Dependent Claim
15 words
The method defined by claim 15 wherein the conductive layer is approximately 500-1,500 Å thick.
Claim 21
Dependent Claim
15 words
The method defined in claim 15 wherein the first silicon layer is 1000-4000 Å thick.
Claim 22
Dependent Claim
16 words
The method defined in claim 13 wherein the second silicon layer is approximately 300-3000 Å thick.
Claim 23
Dependent Claim
18 words
The method defined in claim 13 wherein the third silicon layer is approximately 300-2000 Å thick after planarization.
Claim 24
Dependent Claim
23 words
The method defined by claim 13 wherein the antifuse layer is a silicon dioxide layer with a thickness of approximately <200 Å thick.
Claim 25
Dependent Claim
22 words
The method defined by claim 13 wherein the antifuse layer is a grown silicon dioxide layer grown from the third silicon layer.
Claim 26
Dependent Claim
15 words
The method defined by claim 13 wherein the antifuse layer is a silicon nitride layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-15 | 2006-01-14 | 2006-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-15 | 2010-01-14 | 2010-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-15 | 2014-01-14 | 2014-07-16 | $7700.00 | Window Closed / Lapsed |