Patent US6351411B2 successfully refreshed from Google Patents.
US6351411B2
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Memory using insulator traps
Assignee: Micron Technology Inc
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Filing: 2001-06-12
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Granted: 2002-02-26
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Expires: 2021-06-12
Abstract
Abstract A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.
Inventors
- 👤 Leonard Forbes
- 👤 Joseph E. Geusic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:22
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; B; B82; B82Y; B82Y10/00; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0458; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; H10D30/688; G11C2216/00; G11C2216/02; G11C2216/08; H10D30/69; H10D30/691
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
85 words
A memory device, comprising: an array of memory cells, each memory cell including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 2
Dependent Claim
85 words
A memory device, comprising: an array of memory cells, each memory cell including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 3
Dependent Claim
30 words
The memory device of claim 1 , further comprising a write/erase circuit coupled to the memory cell array and writing data to memory cells in the array of memory cells.
Claim 4
Dependent Claim
21 words
The memory device of claim 1 , wherein the write/erase circuit stores electrons on the trap sites by hot electron injection.
Claim 5
Dependent Claim
20 words
The memory device of claim 1 , wherein the write/erase circuit removes electrons from the trap sites by Price-Sah tunneling.
Claim 6
Dependent Claim
35 words
The memory cell of claim 1 , wherein the trap sites are carried in the gate insulator at an areal concentration that is approximately between 10 12 and 10 15 trap sites per square centimeter.
Claim 7
Dependent Claim
95 words
A computer system, the computer system comprising a memory device, the memory device including: an array of memory cells, each memory cell including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 8
Dependent Claim
95 words
A computer system, the computer system comprising a memory device, the memory device including: an array of memory cells, each memory cell including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 9
Dependent Claim
98 words
A memory device, comprising: an array of memory cells, each memory cell including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator wherein the trap sites are capable of capturing no more than one electron; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 10
Dependent Claim
98 words
A memory device, comprising: an array of memory cells, each memory cell including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator wherein the trap sites are capable of capturing no more than one electron; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 11
Dependent Claim
30 words
The memory device of claim 7 , further comprising a write/erase circuit coupled to the memory cell array and writing data to memory cells in the array of memory cells.
Claim 12
Dependent Claim
21 words
The memory device of claim 7 , wherein the write/erase circuit stores electrons on the trap sites by hot electron injection.
Claim 13
Dependent Claim
20 words
The memory device of claim 7 , wherein the write/erase circuit removes electrons from the trap sites by Price-Sah tunneling.
Claim 14
Dependent Claim
35 words
The memory cell of claim 7 , wherein the trap sites are carried in the gate insulator at an areal concentration that is approximately between 10 12 and 10 15 trap sites per square centimeter.
Claim 15
Dependent Claim
108 words
A computer system, the computer system comprising a memory device, the memory device including: an array of memory cells, each memory cell including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator wherein the trap sites are capable of capturing no more than one electron; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
Claim 16
Dependent Claim
108 words
A computer system, the computer system comprising a memory device, the memory device including: an array of memory cells, each memory cell including a transistor in which a gate insulator carries trap sites at a density such that the trap sites are substantially shielded from each other by intervening portions of the insulator wherein the trap sites are capable of capturing no more than one electron; addressing circuitry coupled to the array of memory cells for accessing individual memory cells in the array of memory cells; and a read circuit coupled to the memory cell array and reading data from memory cells in the array of memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-02-25 | 2005-08-27 | 2006-02-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-02-25 | 2009-08-27 | 2010-02-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-02-25 | 2013-08-27 | 2014-02-26 | $7700.00 | Window Closed / Lapsed |