Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
217 words
A process for fabricating a DRAM capacitor, comprising: providing a substrate having at least one transistor formed thereon; forming an insulation layer on the surface of the substrate, the insulation layer having a contact opening exposing a source/drain region of the transistor; forming a bottom electrode that extends into the contact opening, said forming a bottom electrode comprising: forming a first electrically conductive layer covering the insulation layer and filling the contact opening, with the first electrically conductive layer contacting the exposed source/drain region; naturally forming a native oxide layer on the first electrically conductive layer; forming a second electrically conductive layer on the native oxide layer, the second electrically conductive layer being patterned to form a recess substantially positioned above the location of the contact opening formed in the insulation layer; forming a layer of hemispherical-grain polysilicon over the surface of the second electrically conductive layer and the surface of the recess, the layer of hemispherical-grain polysilicon electrically coupling the second electrically conductive layer to the first electrically conductive layer, the hemispherical-grain polysilicon layer, the second electrically conductive layer, the native oxide layer and the first electrically conductive layer being subsequently patterned to form the bottom electrode; forming a dielectric material layer on the bottom electrode; and forming a top electrode on the dielectric material layer.
Claim 2
Dependent Claim
217 words
A process for fabricating a DRAM capacitor, comprising: providing a substrate having at least one transistor formed thereon; forming an insulation layer on the surface of the substrate, the insulation layer having a contact opening exposing a source/drain region of the transistor; forming a bottom electrode that extends into the contact opening, said forming a bottom electrode comprising: forming a first electrically conductive layer covering the insulation layer and filling the contact opening, with the first electrically conductive layer contacting the exposed source/drain region; naturally forming a native oxide layer on the first electrically conductive layer; forming a second electrically conductive layer on the native oxide layer, the second electrically conductive layer being patterned to form a recess substantially positioned above the location of the contact opening formed in the insulation layer; forming a layer of hemispherical-grain polysilicon over the surface of the second electrically conductive layer and the surface of the recess, the layer of hemispherical-grain polysilicon electrically coupling the second electrically conductive layer to the first electrically conductive layer, the hemispherical-grain polysilicon layer, the second electrically conductive layer, the native oxide layer and the first electrically conductive layer being subsequently patterned to form the bottom electrode; forming a dielectric material layer on the bottom electrode; and forming a top electrode on the dielectric material layer.
Claim 3
Dependent Claim
40 words
The process of fabricating a DRAM capacitor, according to claim 1 , wherein the recess in the second electrically conductive layer is formed by etching in a photolithographic procedure utilizing the native oxide layer as the stopping layer for etching.
Claim 4
Dependent Claim
36 words
The process of fabricating a DRAM capacitor according to claim 2 , wherein the step of forming a recess in the second electrically conductive layer is performed by dry etching in the second electrically conductive layer.
Claim 5
Dependent Claim
22 words
The process of fabricating a DRAM capacitor according to claim 1 , wherein the first electrically conductive layer is doped with impurities.
Claim 6
Dependent Claim
22 words
The process of fabricating a DRAM capacitor according to claim 1 , wherein the second electrically conductive layer is doped with impurities.
Claim 7
Dependent Claim
21 words
The process of fabricating a DRAM capacitor according to claim 1 , wherein the hemispherical-grain polysilicon layer is doped with impurities.
Claim 8
Dependent Claim
195 words
A process of fabricating a bottom electrode of a DRAM capacitor, comprising: providing a substrate having at least one transistor formed thereon; forming an insulation layer on the surface of the substrate, the insulation layer having a contact opening exposing a source/drain region of the transistor; forming a first electrically conductive layer covering the insulation layer and filling the contact opening, with the first electrically conductive layer contacting the exposed source/drain region; forming a native oxide layer over the surface of the first electrically conductive layer; forming a second electrically conductive layer on the native oxide layer; removing a part of the second electrically conductive layer and a part of the native oxide layer to form a recess substantially located above the location of the contact opening formed in the insulation layer, the recess exposing a part of the first electrically conductive layer; and forming a layer of hemispherical-grain polysilicon on the surface of the second electrically conductive layer and the exposed part of the first electrically conductive layer, wherein the bottom electrode of the capacitor comprises the first electrically conductive layer, the native oxide layer, the second electrically conductive layer, and the hemispherical-grain polysilicon.
Claim 9
Dependent Claim
195 words
A process of fabricating a bottom electrode of a DRAM capacitor, comprising: providing a substrate having at least one transistor formed thereon; forming an insulation layer on the surface of the substrate, the insulation layer having a contact opening exposing a source/drain region of the transistor; forming a first electrically conductive layer covering the insulation layer and filling the contact opening, with the first electrically conductive layer contacting the exposed source/drain region; forming a native oxide layer over the surface of the first electrically conductive layer; forming a second electrically conductive layer on the native oxide layer; removing a part of the second electrically conductive layer and a part of the native oxide layer to form a recess substantially located above the location of the contact opening formed in the insulation layer, the recess exposing a part of the first electrically conductive layer; and forming a layer of hemispherical-grain polysilicon on the surface of the second electrically conductive layer and the exposed part of the first electrically conductive layer, wherein the bottom electrode of the capacitor comprises the first electrically conductive layer, the native oxide layer, the second electrically conductive layer, and the hemispherical-grain polysilicon.
Claim 10
Dependent Claim
17 words
The method according to claim 7 , wherein the first electrically conductive layer is doped with impurities.
Claim 11
Dependent Claim
17 words
The method according to claim 7 , wherein the second electrically conductive layer is doped with impurities.