US5902124A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DRAM process
Assignee: United Microelectronics Corp
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Filing: 1997-08-27
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Granted: 1999-05-11
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Expires: 2017-08-27
Abstract
Abstract A high capacitance DRAM structure is provided for a capacitor over bit line DRAM structure. A planarized dielectric layer is provided over the transfer FETs and the bit line contact of a COB structure. A silicon nitride layer is provided over the planarized dielectric layer to serve as an etch stop for a subsequent wet etching process. A first sacrificial oxide layer is deposited over the silicon nitride etch stop layer and then contacts are opened through the various dielectric layers to the appropriate source/drain regions of the transfer FETs. A first polysilicon layer is deposited within the capacitor contact openings and over the first sacrificial oxide layer. A second sacrificial oxide layer is provided and openings are formed in the second sacrificial oxide layer substantially centered over the capacitor contacts. A second polysilicon layer is provided over the second sacrificial oxide layer and in contact with the first polysilicon layer. The lateral extent of polysilicon fins is defined using conventional photolithography and etching on the second polysilicon layer, the second sacrificial oxide layer and the first polysilicon layer in sequence. A wet etch is used to remove the remaining portions of the second sacrificial oxide layer and the first sacrificial oxide layer. The surfaces of the resulting polysilicon fins may be covered with hemispherical grained polysilicon to further increase their surface area. A capacitor dielectric is provided over the fins and an upper capacitor electrode is formed to complete the charge storage capacitor.
Inventors
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:46
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712; H10D1/714
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
185 words
A method of forming a DRAM comprising: providing a substrate having transfer FETs formed in and on the surface of the substrate, the transfer FETs each having first source/drain regions that serve as contacts for charge storage capacitors; providing a dielectric layer over the substrate and the transfer FETs; providing an etch stop layer over the dielectric layer; providing a first sacrificial layer over the etch stop layer; etching through the first sacrificial layer, the etch stop layer and the first dielectric layer to form capacitor contact openings which expose the first source/drain regions; providing vertical conductors within the contact openings and providing a first conductive layer over the first sacrificial layer, the vertical conductors connecting the first conductive layer to the first source/drain regions; patterning the first conductive layer to laterally define the first conductive layer into first conductive fins; removing the first sacrificial layer from below the first conductive fins in a process that stops on and exposes the etch stop layer; providing a capacitor dielectric layer over the first conductive fins; and providing an upper capacitor electrode on the capacitor dielectric layer.
Claim 2
Independent Claim
185 words
A method of forming a DRAM comprising: providing a substrate having transfer FETs formed in and on the surface of the substrate, the transfer FETs each having first source/drain regions that serve as contacts for charge storage capacitors; providing a dielectric layer over the substrate and the transfer FETs; providing an etch stop layer over the dielectric layer; providing a first sacrificial layer over the etch stop layer; etching through the first sacrificial layer, the etch stop layer and the first dielectric layer to form capacitor contact openings which expose the first source/drain regions; providing vertical conductors within the contact openings and providing a first conductive layer over the first sacrificial layer, the vertical conductors connecting the first conductive layer to the first source/drain regions; patterning the first conductive layer to laterally define the first conductive layer into first conductive fins; removing the first sacrificial layer from below the first conductive fins in a process that stops on and exposes the etch stop layer; providing a capacitor dielectric layer over the first conductive fins; and providing an upper capacitor electrode on the capacitor dielectric layer.
Claim 3
Dependent Claim
86 words
The method of claim 1, further comprising the steps of: providing a second sacrificial layer on the first conductive layer; patterning the second sacrificial layer to form openings which expose portions of the first conductive layer; providing a second conductive layer over the second sacrificial layer and in contact with the first conductive layer; patterning the second conductive layer to define the second conductive layer into second conductive fins; and removing the second sacrificial layer from between the second conductive fins and the first conductive fins.
Claim 4
Dependent Claim
20 words
The method of claim 2, wherein the openings in the second sacrificial layer are disposed over the capacitor contact openings.
Claim 5
Dependent Claim
24 words
The method of claim 2, wherein the first and second conductive layers comprise polysilicon and the first and second sacrificial layers comprise an oxide.
Claim 6
Dependent Claim
29 words
The method of claim 3, wherein the steps of removing the first sacrificial layer and of removing the second sacrificial layer are performed in a single wet etching process.
Claim 7
Dependent Claim
18 words
The method of claim 5, wherein the single wet etching process is performed with an etchant comprising HF.
Claim 8
Dependent Claim
24 words
The method of claim 2, further comprising the step of forming a textured surface over the surfaces of the first and second polysilicon fins.
Claim 9
Dependent Claim
29 words
The method of claim 7, wherein the steps of forming a forming a textured surface comprises depositing hemispherical grained polysilicon over surfaces of the first and second polysilicon fins.
Claim 10
Dependent Claim
40 words
The method of claim 8, wherein the hemispherical grained polysilicon is also deposited on the etch stop layer, the method further comprising the step of etching back the hemispherical grained polysilicon to expose the surface of the etch stop layer.
Claim 11
Dependent Claim
30 words
The method of claim 9, wherein the step of etching back the hemispherical grained polysilicon completely removes the hemispherical grained polysilicon from an upper surface of the second polysilicon fin.
Claim 12
Dependent Claim
24 words
The method of claim 2, further comprising the step of planarizing the dielectric layer before providing the etch stop layer over the dielectric layer.
Claim 13
Dependent Claim
17 words
The method of claim 11, wherein the first sacrificial layer is removed in a wet etching process.
Claim 14
Dependent Claim
26 words
The method of claim 12, wherein the first sacrificial layer and the dielectric layer are both oxides and wherein the etch stop layer is silicon nitride.
Claim 15
Independent Claim
246 words
A method of forming a DRAM comprising: providing a substrate having transfer FETs formed in and on the surface of the substrate, the transfer FETs each having first source/drain regions that serve as contacts for charge storage capacitors; providing a dielectric layer over the substrate and the transfer FETs; providing an etch stop layer over the dielectric layer; providing a first oxide layer over the etch stop layer; etching through the first oxide layer, the etch stop layer and the first dielectric layer to form capacitor contact openings which expose the first source/drain regions; providing vertical conductors within the contact openings and providing a first polysilicon layer over the first sacrificial layer, the vertical conductors connecting the first polysilicon layer to the first source/drain regions; providing a second oxide layer on the first polysilicon layer; patterning the second oxide layer to form openings which expose portions of the first polysilicon layer; providing a second polysilicon layer over the second oxide layer and in contact with the first polysilicon layer; patterning the first and second polysilicon layers to laterally define first conductive fins from the first polysilicon layer and second conductive fins from the second polysilicon layer; removing the first and second oxide layers to expose surfaces of the first and second conductive fins in a process which stops on the etch stop layer; providing a capacitor dielectric layer over the first and second conductive fins; and providing an upper capacitor electrode on the capacitor dielectric layer.
Claim 16
Independent Claim
246 words
A method of forming a DRAM comprising: providing a substrate having transfer FETs formed in and on the surface of the substrate, the transfer FETs each having first source/drain regions that serve as contacts for charge storage capacitors; providing a dielectric layer over the substrate and the transfer FETs; providing an etch stop layer over the dielectric layer; providing a first oxide layer over the etch stop layer; etching through the first oxide layer, the etch stop layer and the first dielectric layer to form capacitor contact openings which expose the first source/drain regions; providing vertical conductors within the contact openings and providing a first polysilicon layer over the first sacrificial layer, the vertical conductors connecting the first polysilicon layer to the first source/drain regions; providing a second oxide layer on the first polysilicon layer; patterning the second oxide layer to form openings which expose portions of the first polysilicon layer; providing a second polysilicon layer over the second oxide layer and in contact with the first polysilicon layer; patterning the first and second polysilicon layers to laterally define first conductive fins from the first polysilicon layer and second conductive fins from the second polysilicon layer; removing the first and second oxide layers to expose surfaces of the first and second conductive fins in a process which stops on the etch stop layer; providing a capacitor dielectric layer over the first and second conductive fins; and providing an upper capacitor electrode on the capacitor dielectric layer.
Claim 17
Dependent Claim
22 words
The method of claim 14, wherein the step of removing the first and second oxide layers comprises a single wet etching process.
Claim 18
Dependent Claim
18 words
The method of claim 15, wherein the single wet etching process is performed with an etchant comprising HF.
Claim 19
Dependent Claim
24 words
The method of claim 14, further comprising the step of planarizing the dielectric layer before providing the etch stop layer over the dielectric layer.
Claim 20
Dependent Claim
13 words
The method of claim 17, wherein the etch stop layer is silicon nitride.
Claim 21
Dependent Claim
28 words
The method of claim 14, wherein the first and second polysilicon layers are deposited by CVD and are doped by adding dopants to CVD source gases during deposition.
References Cited (Backward Citations)
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