Method of fabricating a capacitor of dynamic random access memory

Claim 1

A method of fabricating a capacitor of a dynamic random access memory, comprising the steps of: providing a substrate, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of source/drain regions; forming a conductive material on the first dielectric layer so that the conductive material fills the via to contact the one of the source/drain regions; patterning the conductive material to form a first conductive layer; forming a hemispherical polysilicon grain layer at least on the first conductive layer; performing three etching steps including a break-through etching, a main etching, and an overetching, under respective first, second and third different conditions, to etch back the hemispherical polysilicon grain layer so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode; forming a second dielectric layer on the lower electrode; and forming a second conductive layer as an upper electrode on the second dielectric layer.

Claim 2

A method of fabricating a capacitor of a dynamic random access memory, comprising the steps of: providing a substrate, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of source/drain regions; forming a conductive material on the first dielectric layer so that the conductive material fills the via to contact the one of the source/drain regions; patterning the conductive material to form a first conductive layer; forming a hemispherical polysilicon grain layer at least on the first conductive layer; performing three etching steps including a break-through etching, a main etching, and an overetching, under respective first, second and third different conditions, to etch back the hemispherical polysilicon grain layer so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode; forming a second dielectric layer on the lower electrode; and forming a second conductive layer as an upper electrode on the second dielectric layer.

Claim 14

A method of fabricating a capacitor of a dynamic random access memory, comprising the steps of: providing a substrate, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of a plurality of source/drain regions; forming a conductive material on the first dielectric layer so that the conductive material is filled in the via to contact with the one of the source/drain regions; patterning the conductive material to form a first conductive layer; forming a hemispherical polysilicon grain layer at least on the first conductive layer; performing a break through step on the hemispherical polysilicon grain layer, wherein the break through step is performed at a pressure of 60 mT, with a Cl 2 gas flow of 70 sccm, and providing 300 W of electric power for about 10 seconds; performing a main etching step on the hemispherical polysilicon grain layer, wherein the main etching step is performed at a pressure of 60 mT, with a Cl 2 gas flow of 70 sccm and a HBr gas flow of 30 sccm, and providing 300 W of electric power for about 20 seconds; performing an over-etching step on the hemispherical polysilicon grain layer so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode, wherein the over-etching step is performed at a pressure of 120 mT, with a Cl 2 gas flow of 20 sccm, a HBr gas flow of 70 sccm, and a He--O 2 gas flow of 6 sccm, and providing 225 W of electric power for about 15 seconds; forming a second dielectric layer on the lower electrode; and forming a second conductive layer on the second dielectric layer to be an upper electrode.

Claim 15

A method of fabricating a capacitor of a dynamic random access memory, comprising the steps of: providing a substrate, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of a plurality of source/drain regions; forming a conductive material on the first dielectric layer so that the conductive material is filled in the via to contact with the one of the source/drain regions; patterning the conductive material to form a first conductive layer; forming a hemispherical polysilicon grain layer at least on the first conductive layer; performing a break through step on the hemispherical polysilicon grain layer, wherein the break through step is performed at a pressure of 60 mT, with a Cl 2 gas flow of 70 sccm, and providing 300 W of electric power for about 10 seconds; performing a main etching step on the hemispherical polysilicon grain layer, wherein the main etching step is performed at a pressure of 60 mT, with a Cl 2 gas flow of 70 sccm and a HBr gas flow of 30 sccm, and providing 300 W of electric power for about 20 seconds; performing an over-etching step on the hemispherical polysilicon grain layer so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode, wherein the over-etching step is performed at a pressure of 120 mT, with a Cl 2 gas flow of 20 sccm, a HBr gas flow of 70 sccm, and a He--O 2 gas flow of 6 sccm, and providing 225 W of electric power for about 15 seconds; forming a second dielectric layer on the lower electrode; and forming a second conductive layer on the second dielectric layer to be an upper electrode.

Claim 16

A method of fabricating a capacitor of a dynamic random access memory, comprising the steps of: providing a substrate, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of a plurality of source/drain regions; forming a conductive material on the first dielectric layer so that the conductive material fills the via to contact the one of the source/drain regions; patterning the conductive material to form a first conductive layer; forming a hemispherical polysilicon grain layer at least on the first conductive layer; successively performing break through etching, main etching and over-etching, including performing the break through etching on the hemispherical polysilicon grain layer at a first pressure, with a Cl 2 gas flow at a first rate, and with application of electric power of a first wattage for a first duration, then performing the main etching on the hemispherical polysilicon grain layer at a second pressure, with a Cl 2 gas flow at a second rate flow and a flow of another gas at a third rate, and with application of electric power of a second wattage for a second duration greater that the first duration, and then performing the over-etching on the hemispherical polysilicon grain layer at a third pressure greater than the first and second pressures, with a Cl 2 gas flow at a fourth rate, a flow a different gas at a fifth rate ad a flow of still different gas at a sixth rate, and with application of electric power of a third wattage lower than the first and second wattages for a third duration less than the second duration, so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode; forming a second dielectric layer on the lower electrode; and forming a second conductive layer as an upper electrode on the second dielectric layer.

Claim 17

A method of fabricating a capacitor of a dynamic random access memory, comprising the steps of: providing a substrate, wherein a first dielectric layer is formed on the substrate, and a via is formed through the first dielectric layer to expose one of a plurality of source/drain regions; forming a conductive material on the first dielectric layer so that the conductive material fills the via to contact the one of the source/drain regions; patterning the conductive material to form a first conductive layer; forming a hemispherical polysilicon grain layer at least on the first conductive layer; successively performing break through etching, main etching and over-etching, including performing the break through etching on the hemispherical polysilicon grain layer at a first pressure, with a Cl 2 gas flow at a first rate, and with application of electric power of a first wattage for a first duration, then performing the main etching on the hemispherical polysilicon grain layer at a second pressure, with a Cl 2 gas flow at a second rate flow and a flow of another gas at a third rate, and with application of electric power of a second wattage for a second duration greater that the first duration, and then performing the over-etching on the hemispherical polysilicon grain layer at a third pressure greater than the first and second pressures, with a Cl 2 gas flow at a fourth rate, a flow a different gas at a fifth rate ad a flow of still different gas at a sixth rate, and with application of electric power of a third wattage lower than the first and second wattages for a third duration less than the second duration, so that the first conductive layer and the hemispherical polysilicon grain layer together form a lower electrode; forming a second dielectric layer on the lower electrode; and forming a second conductive layer as an upper electrode on the second dielectric layer.