US5874336A
Expired / Lapsed
US
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Method to improve yield for capacitors formed using etchback of polysilicon hemispherical grains
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1997-06-23
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Granted: 1999-02-23
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Expires: 2017-06-23
Abstract
Abstract A method is described for forming capacitor plates with extended surface area using polysilicon hemispherical grains or HSG polysilicon. The HSG polysilicon is formed on the top surface and sidewalls of first capacitor plates. A vertical anisotropic etching step forms an irregular top surface of the first capacitor plates and an anneal step provides good adhesion between the grains of HSG polysilicon and the sidewalls of the first capacitor plates. A timed etchback of the dielectric between the first capacitor plates insures good electrical insulation between adjacent first capacitor plates.
Inventors
- 👤 George Meng-Jaw Cherng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:40
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/712
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
285 words
A method of forming capacitors, comprising the steps of: providing a substrate; forming a layer of first dielectric on said substrate; forming contact holes in said layer of first dielectric; forming a layer of first conductor material on said layer of first dielectric thereby filling said contact holes in said layer of first dielectric; patterning said layer of first conductor material thereby forming a number of first capacitor plates, wherein each said first capacitor plate has a top surface and sidewalls, and spaces between said first capacitor plates wherein those portions of said layer of first dielectric in said spaces are exposed; forming a layer of polysilicon hemispherical grains on said top surface and sidewalls of each said first capacitor plate and said portions of said layer of first dielectric in said spaces between said first capacitor plates; annealing said substrate after forming said layer of hemispherical grains; anisotropically etching said layer of hemispherical grains and said first capacitor plates after annealing said substrate thereby forming an irregular top surface on each said first capacitor plate and removing those portions of said layer of hemispherical grains in said spaces between said first capacitor plates; anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates using said first capacitor plates as a mask; cleaning said substrate after anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates; forming a second dielectric on said irregular top surface and said sidewalls of each said first capacitor plate; and forming a second capacitor plate over said second dielectric formed on said irregular top surface and said sidewalls of each said first capacitor plate.
Claim 2
Independent Claim
285 words
A method of forming capacitors, comprising the steps of: providing a substrate; forming a layer of first dielectric on said substrate; forming contact holes in said layer of first dielectric; forming a layer of first conductor material on said layer of first dielectric thereby filling said contact holes in said layer of first dielectric; patterning said layer of first conductor material thereby forming a number of first capacitor plates, wherein each said first capacitor plate has a top surface and sidewalls, and spaces between said first capacitor plates wherein those portions of said layer of first dielectric in said spaces are exposed; forming a layer of polysilicon hemispherical grains on said top surface and sidewalls of each said first capacitor plate and said portions of said layer of first dielectric in said spaces between said first capacitor plates; annealing said substrate after forming said layer of hemispherical grains; anisotropically etching said layer of hemispherical grains and said first capacitor plates after annealing said substrate thereby forming an irregular top surface on each said first capacitor plate and removing those portions of said layer of hemispherical grains in said spaces between said first capacitor plates; anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates using said first capacitor plates as a mask; cleaning said substrate after anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates; forming a second dielectric on said irregular top surface and said sidewalls of each said first capacitor plate; and forming a second capacitor plate over said second dielectric formed on said irregular top surface and said sidewalls of each said first capacitor plate.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein said first conductor material is doped polysilicon.
Claim 4
Dependent Claim
16 words
The method of claim 2 wherein said doped polysilicon is polysilicon doped with phosphorous or arsenic.
Claim 5
Dependent Claim
15 words
The method of claim 1 wherein said first dielectric is an oxide or silicon nitride.
Claim 6
Dependent Claim
23 words
The method of claim 1 wherein said annealing said substrate is carried out at a temperature of between about 700° and 1000° C.
Claim 7
Dependent Claim
42 words
The method of claim 1 wherein said polysilicon hemispherical grains are formed by means of low pressure chemical vapor deposition using silane at a temperature of between about 500° and 600° C. and a pressure of between about 0.01 and 0.5 Torr.
Claim 8
Dependent Claim
20 words
The method of claim 1 wherein said polysilicon hemispherical grains are formed of phosphorous doped polysilicon or arsenic doped polysilicon.
Claim 9
Dependent Claim
15 words
The method of claim 1 wherein cleaning said substrate is accomplished using dilute hydrofluoric acid.
Claim 10
Dependent Claim
24 words
The method of claim 1 wherein said anisotropically etching said layer of hemispherical grains consists of vertically anisotropically etching said layer of hemispherical grains.
Claim 11
Dependent Claim
46 words
The method of claim 1 wherein said anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates consists of vertically anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates.
Claim 12
Dependent Claim
18 words
The method of claim 1 wherein said substrate is a silicon integrated circuit wafer having devices formed therein.
Claim 13
Independent Claim
297 words
A method of forming capacitors, comprising the steps of: providing an integrated circuit wafer having devices formed therein; forming a layer of first dielectric on said substrate; forming contact holes in said layer of first dielectric; forming a layer of doped polysilicon on said layer of first dielectric thereby filling said contact holes in said layer of first dielectric; patterning said layer of doped polysilicon thereby forming a number of first capacitor plates, wherein each said first capacitor plate has a top surface and sidewalls, and spaces between said first capacitor plates wherein those portions of said layer of first dielectric in said spaces are exposed; forming a layer of polysilicon hemispherical grains on said top surface and sidewalls of each said first capacitor plate and said portions of said layer of first dielectric in said spaces between said first capacitor plates; annealing said integrated circuit wafer after forming said layer of polysilicon hemispherical grains; anisotropically etching said layer of polysilicon hemispherical grains and said capacitor plates after annealing said integrated circuit wafer thereby forming an irregular top surface on each said first capacitor plate and removing those portions of said layer of polysilicon hemispherical grains in said spaces between said first capacitor plates; anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates using said first capacitor plates as a mask; cleaning said integrated circuit wafer after anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates; forming a second dielectric on said irregular top surface and said sidewalls of each said first capacitor plate; and forming a second capacitor plate over said second dielectric formed on said irregular top surface and said sidewalls of each said first capacitor plate.
Claim 14
Independent Claim
297 words
A method of forming capacitors, comprising the steps of: providing an integrated circuit wafer having devices formed therein; forming a layer of first dielectric on said substrate; forming contact holes in said layer of first dielectric; forming a layer of doped polysilicon on said layer of first dielectric thereby filling said contact holes in said layer of first dielectric; patterning said layer of doped polysilicon thereby forming a number of first capacitor plates, wherein each said first capacitor plate has a top surface and sidewalls, and spaces between said first capacitor plates wherein those portions of said layer of first dielectric in said spaces are exposed; forming a layer of polysilicon hemispherical grains on said top surface and sidewalls of each said first capacitor plate and said portions of said layer of first dielectric in said spaces between said first capacitor plates; annealing said integrated circuit wafer after forming said layer of polysilicon hemispherical grains; anisotropically etching said layer of polysilicon hemispherical grains and said capacitor plates after annealing said integrated circuit wafer thereby forming an irregular top surface on each said first capacitor plate and removing those portions of said layer of polysilicon hemispherical grains in said spaces between said first capacitor plates; anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates using said first capacitor plates as a mask; cleaning said integrated circuit wafer after anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates; forming a second dielectric on said irregular top surface and said sidewalls of each said first capacitor plate; and forming a second capacitor plate over said second dielectric formed on said irregular top surface and said sidewalls of each said first capacitor plate.
Claim 15
Dependent Claim
15 words
The method of claim 12 wherein said first dielectric is an oxide or silicon nitride.
Claim 16
Dependent Claim
25 words
The method of claim 12 wherein said annealing said integrated circuit wafer is carried out at a temperature of between about 700° and 1000° C.
Claim 17
Dependent Claim
42 words
The method of claim 12 wherein said polysilicon hemispherical grains are formed by means of low pressure chemical vapor deposition using silane at a temperature of between about 500° and 600° C. and a pressure of between about 0.01 and 0.5 Torr.
Claim 18
Dependent Claim
17 words
The method of claim 12 wherein cleaning said integrated circuit wafer is accomplished using dilute hydrofluoric acid.
Claim 19
Dependent Claim
15 words
The method of claim 12 wherein said doped polysilicon is doped with phosphorous or arsenic.
Claim 20
Dependent Claim
16 words
The method of claim 12 wherein said polysilicon hemispherical grains are doped with phosphorous or arsenic.
Claim 21
Dependent Claim
26 words
The method of claim 12 wherein said anisotropically etching said layer of polysilicon hemispherical grains consists of vertically anisotropically etching said layer of polysilicon hemispherical grains.
Claim 22
Dependent Claim
46 words
The method of claim 12 wherein said anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates consists of vertically anisotropically etching said portions of said layer of first dielectric in said spaces between said first capacitor plates.
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