US6200839B1
Expired / Lapsed
US
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Methods of forming thin film transistors
Assignee: Micron Technology Inc
•
Filing: 1999-07-06
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Granted: 2001-03-13
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Expires: 2019-07-06
Abstract
Abstract A method of forming a thin film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.
Inventors
- 👤 Shubneesh Batra
- 👤 Monte Manning
- 👤 Sanjay Banerjee
- 👤 LeTien Jung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6729; H10D30/6737; H10D30/6739; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01322
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
131 words
A method of forming a transistor device, comprising: forming a gate over a first semiconductive material to define a channel region within the first semiconductive material, the gate having a pair of opposing sidewall edges; forming at least one electrically conductive sidewall spacer over at least one of the sidewall edges of the gate, the providing the spacer comprising: providing an amorphous second semiconductive material layer over the gate; anisotropically etching the second semiconductive material layer to form opposing sidewall spacers laterally adjacent the gate; and converting the amorphous layer to polycrystalline form after deposition of the amorphous layer; and after providing the sidewall spacer, subjecting the first semiconductive material to conductivity doping effective to form an electrically conductive source region and an electrically conductive drain region proximate the channel region.
Claim 2
Independent Claim
131 words
A method of forming a transistor device, comprising: forming a gate over a first semiconductive material to define a channel region within the first semiconductive material, the gate having a pair of opposing sidewall edges; forming at least one electrically conductive sidewall spacer over at least one of the sidewall edges of the gate, the providing the spacer comprising: providing an amorphous second semiconductive material layer over the gate; anisotropically etching the second semiconductive material layer to form opposing sidewall spacers laterally adjacent the gate; and converting the amorphous layer to polycrystalline form after deposition of the amorphous layer; and after providing the sidewall spacer, subjecting the first semiconductive material to conductivity doping effective to form an electrically conductive source region and an electrically conductive drain region proximate the channel region.
Claim 3
Dependent Claim
17 words
The method of claim 1 wherein the first semiconductive material and second semiconductive material are both silicon.
Claim 4
Independent Claim
102 words
A method of forming a transistor, comprising: forming a gate having a conductivity enhancing impurity over a first semiconductive material to define a channel region within the semiconductive material; providing an undoped second semiconductive material spacer-forming layer over the gate; anisotropically etching the spacer-forming layer to form opposing sidewall spacers laterally adjacent the gate; after providing the sidewall spacers, subjecting the first semiconductive material to conductivity doping effective to form an electrically conductive source region and an electrically conductive drain region proximate the channel region; and rendering the sidewall spacers electrically conductive substantially by out-diffusion of conductivity enhancing impurity from the gate.
Claim 5
Independent Claim
102 words
A method of forming a transistor, comprising: forming a gate having a conductivity enhancing impurity over a first semiconductive material to define a channel region within the semiconductive material; providing an undoped second semiconductive material spacer-forming layer over the gate; anisotropically etching the spacer-forming layer to form opposing sidewall spacers laterally adjacent the gate; after providing the sidewall spacers, subjecting the first semiconductive material to conductivity doping effective to form an electrically conductive source region and an electrically conductive drain region proximate the channel region; and rendering the sidewall spacers electrically conductive substantially by out-diffusion of conductivity enhancing impurity from the gate.
Claim 6
Dependent Claim
17 words
The method of claim 3 wherein the first semiconductive material and second semiconductive material are both silicon.
Claim 7
Independent Claim
131 words
A method of forming a thin film transitor comprising the following steps: forming a transistor gate relative to a substrate; providing at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the providing the spacer comprising: forming an amorphous silicon material layer over the gate; anisotropically etching the silicon layer to form opposing sidewall spacers laterally adjacent the gate; and converting the amorphous silicon layer to polycrystalline form after deposition of the amorphous layer; and providing a thin film transistor layer of polycrystalline silicon over the gate and sidewall spacer; and providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region positioned operatively over the one electrically conductive sidewall spacer.
Claim 8
Independent Claim
131 words
A method of forming a thin film transitor comprising the following steps: forming a transistor gate relative to a substrate; providing at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the providing the spacer comprising: forming an amorphous silicon material layer over the gate; anisotropically etching the silicon layer to form opposing sidewall spacers laterally adjacent the gate; and converting the amorphous silicon layer to polycrystalline form after deposition of the amorphous layer; and providing a thin film transistor layer of polycrystalline silicon over the gate and sidewall spacer; and providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region positioned operatively over the one electrically conductive sidewall spacer.
Claim 9
Independent Claim
115 words
A method of forming a thin film transistor comprising the following steps: forming a transistor gate having a conductivity enhancing impurity relative to a substrate; providing an undoped silicon spacer-forming layer over the gate; anisotropically etching the spacer-forming layer to form opposing sidewall spacers laterally adjacent the gate; providing a thin film transistor layer of polycrystalline silicon over the gate and sidewall spacers; providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned over one of the electrically conductive sidewall spacers; and rendering the sidewall spacers electrically conductive substantially by out-diffusion of conductivity enhancing impurity from the gate.
Claim 10
Independent Claim
115 words
A method of forming a thin film transistor comprising the following steps: forming a transistor gate having a conductivity enhancing impurity relative to a substrate; providing an undoped silicon spacer-forming layer over the gate; anisotropically etching the spacer-forming layer to form opposing sidewall spacers laterally adjacent the gate; providing a thin film transistor layer of polycrystalline silicon over the gate and sidewall spacers; providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned over one of the electrically conductive sidewall spacers; and rendering the sidewall spacers electrically conductive substantially by out-diffusion of conductivity enhancing impurity from the gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-12 | 2004-09-11 | 2005-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-12 | 2008-09-11 | 2009-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-12 | 2012-09-11 | 2013-03-13 | $7700.00 | Window Closed / Lapsed |