Abstract A novel structure of a polycrystalline silicon thin film transistor manifested in a drain offset region and a sub-gate structure. The drain offset region is formed between a channel region and a drain region in the polycrystalline silicon thin film. The sub-gate structure comprises at least one sub-gate, except for a main gate which is provided in a normal field effect transistor. This structure is applicable to either an upper gate type or a bottom gate type thin film transistor. The sub-gate structure may include an upper sub-gate and/or a bottom sub-gate. The upper sub-gate overlays the channel region, drain offset and drain regions through an insulation layer. The bottom sub-gate underlies the channel region, drain offset and drain regions through an insulation layer. The sub-gate is applied with the same voltage or less as the drain voltage thereby permitting a relaxation of a high field concentration caused at a drain junction to be realized. This may provide a reduction of a leakage current and a security of a high ON-current.
A thin film transistor comprising: source and drain regions of one conductivity type provided over an insulation layer; a channel region of a conductivity type opposite to said one conductivity type abutting said source region; a drain offset region of said conductivity type opposite to said one conductivity type provided between said drain and channel regions; a main gate provided under said channel region through a gate insulation film, said main gate being provided on said insulation layer; and a sub-gate structure comprising at least one sub-gate isolated from each of said source, drain, channel and drain offset regions, said sub-gate structure controlling a potential at least in said channel region and said drain offset region, and overlapping with at least a portion of said main gate and the entirety of said channel region.
Claim 2
Dependent Claim
134 words
A thin film transistor comprising: source and drain regions of one conductivity type provided over an insulation layer; a channel region of a conductivity type opposite to said one conductivity type abutting said source region; a drain offset region of said conductivity type opposite to said one conductivity type provided between said drain and channel regions; a main gate provided under said channel region through a gate insulation film, said main gate being provided on said insulation layer; and a sub-gate structure comprising at least one sub-gate isolated from each of said source, drain, channel and drain offset regions, said sub-gate structure controlling a potential at least in said channel region and said drain offset region, and overlapping with at least a portion of said main gate and the entirety of said channel region.
Claim 3
Dependent Claim
26 words
The thin film transistor as claimed in claim 1, wherein said source, drain, channel and drain offset regions each comprise a single polycrystalline silicon thin film.
Claim 4
Dependent Claim
29 words
The thin film transistor as claimed in claim 1, wherein said sub-gate structure comprises an upper sub-gate overlaying said channel, drain offset and drain regions through an isolation film.