US5358879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making gate overlapped lightly doped drain for buried channel devices
Assignee: Lockheed Martin Corp
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Filing: 1993-04-30
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Granted: 1994-10-25
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Expires: 2013-04-30
Abstract
Abstract A process to form poly sidegate LDD structures on buried channel MOSFETs is described. A polysilicon spacer is formed on the gate after source/drain processing. The spacer is later shorted to the main gate by implantation of neutral impurities. The process is particularly suited for SOI technology.
Inventors
- 👤 Frederick T. Brady
- 👤 Charles P. Breiten
- 👤 Nadium F. Haddad
- 👤 William G. Houston
- 👤 Oliver S. Spencer
- 👤 Steven J. Wright
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01354; H10D64/021; H10D64/60; H10D64/66; H10D64/671; Y; Y10; Y10S; Y10S148/00; Y10S148/114
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
131 words
A method of fabricating a semiconductor device, comprising the steps of: forming a transistor structure having a gate electrode, source and drain regions and a gate oxide on a semiconductor substrate; forming a nitride cap on an oxide layer over the gate electrode; implanting first ions into the substrate to form an LDD layer in the substrate; forming a nitride spacer over the gate electrode; implanting second ions into the substrate to form source and drain regions containing the LDD layer; stripping nitride cap and spacer material; forming a polysilicon sidegate adjacent to the gate electrode; forming a second nitride spacer adjacent to the polysilicon sidegates; and implanting heavy ions of a neutral conductivity type in silicon into the gate region to electrically short the gate electrode and polysilicon sidegate together.
Claim 2
Independent Claim
131 words
A method of fabricating a semiconductor device, comprising the steps of: forming a transistor structure having a gate electrode, source and drain regions and a gate oxide on a semiconductor substrate; forming a nitride cap on an oxide layer over the gate electrode; implanting first ions into the substrate to form an LDD layer in the substrate; forming a nitride spacer over the gate electrode; implanting second ions into the substrate to form source and drain regions containing the LDD layer; stripping nitride cap and spacer material; forming a polysilicon sidegate adjacent to the gate electrode; forming a second nitride spacer adjacent to the polysilicon sidegates; and implanting heavy ions of a neutral conductivity type in silicon into the gate region to electrically short the gate electrode and polysilicon sidegate together.
Claim 3
Dependent Claim
13 words
The method of claim 1 wherein the device is a buried channel MOSFET.
Claim 4
Dependent Claim
14 words
The method of claim 2 wherein the device is formed on a SOI substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-24 | 1998-04-25 | 1998-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-24 | 2002-04-25 | 2002-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-24 | 2006-04-25 | 2006-10-25 | $7700.00 | Window Closed / Lapsed |