Method of constructing lightly doped drain (LDD) integrated circuit structure

Claim 2

An improved method for forming one or more LDD regions in an integrated circuit structure wherein there is no offset between the gate electrode and the source and drain regions in the resulting structure which comprises: (a) forming a polysilicon gate electrode over a gate oxide layer previously formed on a semiconductor wafer substrate; (b) doping said substrate to form one or more LDD regions; (c) selectively depositing polysilicon on the polysilicon sidewalls of said polysilicon gate electrode; and (d) doping said substrate to form source and drain regions in said substrate using said selectively deposited polysilicon as a mask over said LDD regions previously formed in said substrate.

Claim 3

The method of claim 1 wherein said step of forming said polysilicon gate electrode further comprises forming an oxide layer over the top surface of a polysilicon layer prior to patterning said layers to form said polysilicon gate electrode.

Claim 4

The method of claim 2 wherein said step of doping said substrate to form said one or more LDD regions further comprises implanting said substrate with a N- dopant.

Claim 5

The method of claim 2 wherein said step of doping said substrate to form said one or more LDD regions further comprises implanting said substrate with phosphorus at a dopant concentration of from about 10 13 to about 10 14 atoms/cm to form one or more N- LDD regions in said substrate.

Claim 6

The method of claim 3 including the further step of annealing said semiconductor wafer substrate after said step of implanting said N- dopant to diffuse said N- dopant into said substrate.

Claim 7

The method of claim 3 including the further step of annealing said semiconductor wafer substrate, after said step of implanting said N- dopant, at a temperature of from about 850° C. to about 950° C. for a period of from about 15 minutes to about 30 minutes to diffuse said N- dopant into said substrate.

Claim 8

The method of claim 3 including the further step of annealing said semiconductor wafer substrate, after said step of implanting said N- dopant, at a temperature of from about 950° C. to about 1050° C. for a period of from about 10 seconds to about 30 seconds to diffuse said N- dopant into said substrate by a rapid anneal process.

Claim 9

The method of claim 3 wherein said step of doping said substrate to form said source and drain regions in said substrate further comprises implanting said substrate with an N+ dopant.

Claim 10

The method of claim 8 including the further step of annealing said semiconductor wafer substrate, after said step of implanting said N+ dopant, to diffuse said N- dopant and said N+ dopant into said substrate.

Claim 11

The method of claim 1 wherein said step of selectively forming said polysilicon on the sidewalls of said polysilicon gate electrode further comprises depositing polysilicon on said polysilicon gate electrode sidewalls in a CVD chamber at a pressure of from about 10 Torr to about 760 Torr, using a halogen-containing source of silicon which is flowed into the CVD vacuum chamber at a flow rate of from about 100 sccm to about 200 sccm.

Claim 12

The method of claim 10 wherein said polysilicon is selectively deposited on the sidewalls of said polysilicon gate electrode until a polysilicon deposit having a lateral thickness or width of from about 0.05 micrometers to about 0.2 micrometers has deposited on the polysilicon sidewalls of said gate electrode.

Claim 13

The method of claim 10 wherein said halogen-containing source of silicon is selected from the class consisting of SiH 2 Cl 2 , SiHCl 3 , and SiCl 4 .

Claim 14

An improved method for forming one or more LDD regions in an integrated circuit structure wherein there is no offset between the gate electrode and the source and drain regions in the resulting structure which comprises: (a) forming a gate oxide layer on a semiconductor wafer substrate; (b) forming a polysilicon layer over said gate oxide layer; (c) forming a further oxide layer over said polysilicon layer; (d) patterning said further oxide layer and said polysilicon layer to form a polysilicon gate electrode on said wafer substrate; (e) doping said substrate with an N- dopant at a dopant concentration of from about 10 13 to about 10 14 atoms/cm 2 to form one or more N-LDD regions in said substrate; (f) selectively depositing polysilicon on the polysilicon sidewalls of said gate electrode in a CVD chamber at a pressure of from about 10 Torr to about 760 Torr, using a halogen-containing source of silicon which is flowed into the CVD chamber at a flow rate of from about 100 sccm to about 200 sccm; (g) doping said substrate with an N+ dopant at a dopant concentration of from about 2×10 15 to about 5×10 15 atoms/cm 2 to form N+ source and drain regions in said substrate using said selectively deposited polysilicon as a mask over said LDD regions previously formed in said substrate; and (h) annealing said implanted substrate at a temperature of from about 850° C. to about 950° C. for a period of from about 15 minutes to about 30 minutes or at a temperature of from about 950° C. to about 1050° C. for a period of from about 10 seconds to about 30 seconds to diffuse said dopants into said substrate.

Claim 15

An improved method for forming one or more LDD regions in an integrated circuit structure wherein there is no offset between the gate electrode and the source and drain regions in the resulting structure which comprises: (a) forming a gate oxide layer on a semiconductor wafer substrate; (b) forming a polysilicon layer over said gate oxide layer; (c) forming a further oxide layer over said polysilicon layer; (d) patterning said further oxide layer and said polysilicon layer to form a polysilicon gate electrode on said wafer substrate; (e) doping said substrate with an N- dopant at a dopant concentration of from about 10 13 to about 10 14 atoms/cm 2 to form one or more N-LDD regions in said substrate; (f) selectively depositing polysilicon on the polysilicon sidewalls of said gate electrode in a CVD chamber at a pressure of from about 10 Torr to about 760 Torr, using a halogen-containing source of silicon which is flowed into the CVD chamber at a flow rate of from about 100 sccm to about 200 sccm; (g) doping said substrate with an N+ dopant at a dopant concentration of from about 2×10 15 to about 5×10 15 atoms/cm 2 to form N+ source and drain regions in said substrate using said selectively deposited polysilicon as a mask over said LDD regions previously formed in said substrate; and (h) annealing said implanted substrate at a temperature of from about 850° C. to about 950° C. for a period of from about 15 minutes to about 30 minutes or at a temperature of from about 950° C. to about 1050° C. for a period of from about 10 seconds to about 30 seconds to diffuse said dopants into said substrate.

Claim 16

The method of claim 13 wherein said step of doping said substrate to form said one or more N-LDD regions in said substrate further comprises implanting said substrate with phosphorus to form said one or more N- LDD regions in said substrate.

Claim 17

The method of claim 13 wherein said step of doping said substrate to form said N+ source and drain regions in said substrate further comprises implanting said substrate with arsenic to form said one or more N+ source and drain regions in said substrate.

Claim 18

The method of claim 13 wherein said polysilicon is selectively deposited on the sidewalls of said polysilicon gate electrode until a polysilicon deposit having a lateral thickness or width of from about 0.05 micrometers to about 0.2 micrometers has deposited on the polysilicon sidewalls of said gate electrode.

Claim 19

The method of claim 13 wherein said halogen-containing source of silicon is selected from the class consisting of SiH 2 Cl 2 , SiHCl 3 , and SiCl 4 .

Claim 20

An improved method for forming one or more LDD regions in an integrated circuit structure wherein there is no offset between the gate electrode and the source and drain regions in the resulting structure which comprises: (a) forming a gate oxide layer on a semiconductor wafer substrate; (b) forming a polysilicon layer over said gate oxide layer; (c) forming a further oxide layer over said polysilicon layer; (d) patterning said further oxide layer and said polysilicon layer to form a polysilicon gate electrode on said wafer substrate; (e) implanting said substrate with phosphorus at a dopant concentration of from about 10 13 to about 10 14 atoms/cm 2 and an energy level of from about 60 KeV to about 80 KeV to form one or more N- LDD regions in said substrate; (f) selectively depositing polysilicon on the polysilicon sidewalls of said gate electrode in a CVD chamber at a pressure of from about 10 Torr to about 760 Torr, using a halogen-containing source of silicon selected from the class consisting of SiH 2 Cl 2 , SiHCl 3 , and SiCl 4 which is flowed into the CVD vacuum chamber at a flow rate of from about 100 sccm to about 200 sccm until a polysilicon deposit having a lateral thickness or width of from about 0.05 micrometers to about 0.2 micrometers has deposited on the polysilicon sidewalls of said gate electrode; (g) implanting said substrate with arsenic at a dopant concentration of from about 2×10 15 to about 5×10 15 atoms/cm 2 and an energy level of from about 60 KeV to about 80 KeV to form N+ source and drain regions in said substrate using said selectively deposited polysilicon as a mask over said LDD regions previously formed in said substrate; and (h) annealing said implanted substrate at a temperature of from about 850° C. to about 950° C. for a period of from about 15 minutes to about 30 minutes or at a temperature of from about 950° C. to about 1050° C. for a period of from about 10 seconds to diffuse said dopants into said substrate.

Claim 21

An improved method for forming one or more LDD regions in an integrated circuit structure wherein there is no offset between the gate electrode and the source and drain regions in the resulting structure which comprises: (a) forming a gate oxide layer on a semiconductor wafer substrate; (b) forming a polysilicon layer over said gate oxide layer; (c) forming a further oxide layer over said polysilicon layer; (d) patterning said further oxide layer and said polysilicon layer to form a polysilicon gate electrode on said wafer substrate; (e) implanting said substrate with phosphorus at a dopant concentration of from about 10 13 to about 10 14 atoms/cm 2 and an energy level of from about 60 KeV to about 80 KeV to form one or more N- LDD regions in said substrate; (f) selectively depositing polysilicon on the polysilicon sidewalls of said gate electrode in a CVD chamber at a pressure of from about 10 Torr to about 760 Torr, using a halogen-containing source of silicon selected from the class consisting of SiH 2 Cl 2 , SiHCl 3 , and SiCl 4 which is flowed into the CVD vacuum chamber at a flow rate of from about 100 sccm to about 200 sccm until a polysilicon deposit having a lateral thickness or width of from about 0.05 micrometers to about 0.2 micrometers has deposited on the polysilicon sidewalls of said gate electrode; (g) implanting said substrate with arsenic at a dopant concentration of from about 2×10 15 to about 5×10 15 atoms/cm 2 and an energy level of from about 60 KeV to about 80 KeV to form N+ source and drain regions in said substrate using said selectively deposited polysilicon as a mask over said LDD regions previously formed in said substrate; and (h) annealing said implanted substrate at a temperature of from about 850° C. to about 950° C. for a period of from about 15 minutes to about 30 minutes or at a temperature of from about 950° C. to about 1050° C. for a period of from about 10 seconds to diffuse said dopants into said substrate.

Claim 22

An improved MOS integrated circuit structure characterized by the formation of one or more N-LDD regions in a semiconductor wafer substrate beneath a polysilicon gate electrode and source and drain regions in said substrate self-aligned to the edges of said gate electrode, wherein a polysilicon gate electrode is first formed over said substrate, said substrate is doped with an N- dopant to form said one or more LDD regions, further polysilicon is selectively deposited only on the polysilicon sidewalls of said gate electrode, and said substrate is then doped with an N+ dopant to form source and drain regions self-aligned to the edge of said polysilicon gate electrode using said selectively deposited polysilicon as a mask over said one or more N- LDD regions.

Claim 23

An improved MOS integrated circuit structure characterized by the formation of one or more N-LDD regions in a semiconductor wafer substrate beneath a polysilicon gate electrode and source and drain regions in said substrate self-aligned to the edges of said gate electrode, wherein a polysilicon gate electrode is first formed over said substrate, said substrate is doped with an N- dopant to form said one or more LDD regions, further polysilicon is selectively deposited only on the polysilicon sidewalls of said gate electrode, and said substrate is then doped with an N+ dopant to form source and drain regions self-aligned to the edge of said polysilicon gate electrode using said selectively deposited polysilicon as a mask over said one or more N- LDD regions.