Abstract Hot electron injection into the gate oxides of MOSFET devices imposes limitations on the miniaturization of such devices in VLSI circuits. A buried channel with a surface spacer is provided to guard against hot electron trapping effects while preserving process and structure compatibility with micron or submicron VLSI devices. The channel current is redirected into a buried channel at a distance away from the interface in the vicinity of the drain region where the hot electron effect is most likely to occur. Additionally, a surface implant is performed to improve any gate control that may be lost as a result of the buried channel so as to mitigate any degradition of the current-voltage characteristics of the device.
A method for producing source or drain region structures in field effect transistor devices, said method comprising the steps of: (a) implanting a light concentration of a first polarity dopant a fixed distance beneath the surface of a semiconductor body; (b) implanting a second light dopant concentration of the same first polarity adjacent to the surface of said semiconductor body and spaced vertically apart from said region of dopant implanted a fixed distance beneath said semiconductor surface; and (c) forming a source or drain region in said semiconductor body, said source or drain region including a heavy concentration of said first polarity dopant and extending downwardly from the surface of said semiconductor body so as to include said lighter doped region and extending horizontally, said horizontal extension of said source or drain region being limited by implant screen means so as to define lighter doped protrusions extending from said heavily doped source or drain region, said light concentration being substantially smaller than said heavy concentration.
Claim 2
Independent Claim
165 words
A method for producing source or drain region structures in field effect transistor devices, said method comprising the steps of: (a) implanting a light concentration of a first polarity dopant a fixed distance beneath the surface of a semiconductor body; (b) implanting a second light dopant concentration of the same first polarity adjacent to the surface of said semiconductor body and spaced vertically apart from said region of dopant implanted a fixed distance beneath said semiconductor surface; and (c) forming a source or drain region in said semiconductor body, said source or drain region including a heavy concentration of said first polarity dopant and extending downwardly from the surface of said semiconductor body so as to include said lighter doped region and extending horizontally, said horizontal extension of said source or drain region being limited by implant screen means so as to define lighter doped protrusions extending from said heavily doped source or drain region, said light concentration being substantially smaller than said heavy concentration.
Claim 3
Dependent Claim
11 words
The method of claim 1 in which said dopant is arsenic.
Claim 4
Dependent Claim
14 words
The method of claim 1 in which step (a) is performed before step (b).
Claim 5
Dependent Claim
14 words
The method of claim 1 in which step (b) is performed before step (a).
Claim 6
Dependent Claim
28 words
The method of claim 1 in which step (a) is performed at an implant dosage of between about 10 12 and 10 14 dopant atoms per square centimeter.
Claim 7
Dependent Claim
28 words
The method of claim 1 in which step (b) is preformed at an implant dosage of between about 10 12 and 10 14 dopant atoms per square centimeter.
Claim 8
Dependent Claim
24 words
The method of claim 1 in which step (c) is performed at an implant dosage of about 8×10 15 dopant atoms per square centimeter.