Patent US6180443B1 successfully refreshed from Google Patents.
US6180443B1
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Semiconductor device and method of fabricating the same
Assignee: SK Hynix Inc
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Filing: 1998-09-18
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Granted: 2001-01-30
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Expires: 2018-09-18
Abstract
Abstract A semiconductor device having a plurality of transistors connected in series in a semiconductor substrate, the device includes first and second gate electrodes on the semiconductor substrate, a punch-through stop layer in the semiconductor substrate below the first gate electrode at a predetermined depth, and first, second, and third heavily doped impurity regions in the semiconductor substrate at both sides of the first and second gate electrodes.
Inventors
- 👤 Dae Gwan Kang
- 👤 Chang Yong Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:56
CPC Classifications
H; H10; H10P; H10P10/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/013; H10D84/0133; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
154 words
A method of fabricating a semiconductor device having first and second transistors connected in series in a semiconductor substrate, the method comprising the steps of: forming an insulating film pattern on the semiconductor substrate such that a first region of the semiconductor substrate is exposed and a second region of the semiconductor substrate is covered; forming a punch-through stop layer by implanting impurity ions in the first region of the semiconductor substrate, the second region of the semiconductor substrate being masked from the impurity ions by the insulating film pattern; forming first and second gate electrodes respectively on the first and second regions of the semiconductor substrate, the first gate electrode located over the punch-through stop layer; and forming first, second, and third heavily doped impurity regions in the semiconductor substrate at sides of the first and second gate electrodes, wherein the first and second transistors are both one of NMOS and PMOS transistors.
Claim 2
Independent Claim
154 words
A method of fabricating a semiconductor device having first and second transistors connected in series in a semiconductor substrate, the method comprising the steps of: forming an insulating film pattern on the semiconductor substrate such that a first region of the semiconductor substrate is exposed and a second region of the semiconductor substrate is covered; forming a punch-through stop layer by implanting impurity ions in the first region of the semiconductor substrate, the second region of the semiconductor substrate being masked from the impurity ions by the insulating film pattern; forming first and second gate electrodes respectively on the first and second regions of the semiconductor substrate, the first gate electrode located over the punch-through stop layer; and forming first, second, and third heavily doped impurity regions in the semiconductor substrate at sides of the first and second gate electrodes, wherein the first and second transistors are both one of NMOS and PMOS transistors.
Claim 3
Dependent Claim
66 words
The method according to claim 1 , wherein the step of forming the punch-through stop layer comprises the steps of: successively forming first and second insulating layers on the semiconductor substrate; selectively removing the second insulating layer and the first insulating layer to expose a portion of the semiconductor substrate; and implanting the impurity ions into the exposed portion of semiconductor substrate to prevent a punch-through.
Claim 4
Dependent Claim
22 words
The method according to claim 2 , wherein the first insulating layer is formed by oxidizing a surface of the semiconductor substrate.
Claim 5
Dependent Claim
16 words
The method according to claim 2 , wherein the second insulating layer is formed of nitride.
Claim 6
Dependent Claim
42 words
The method according to claim 2 , wherein the step of implanting impurity ions is executed by an implanting energy of 20˜50 KeV and a dosage of 1×10 12 ˜5×10 13 /cm 2 when the first and second transistors are NMOS transistors.
Claim 7
Dependent Claim
13 words
The method according to claim 5 , wherein the impurity ions include boron.
Claim 8
Dependent Claim
42 words
The method according to claim 2 , wherein the step of implanting impurity ions is executed by an implanting energy of 60˜100 KeV and a dosage of 1×10 12 ˜5×10 13 /cm 2 when the first and second transistors are PMOS transistors.
Claim 9
Dependent Claim
13 words
The method according to claim 7 , wherein the impurity ions include phosphorus.
Claim 10
Dependent Claim
42 words
The method according to claim 2 , wherein the step of implanting impurity ions is executed by an implanting energy of 140˜200 KeV and a dosage of 1×10 12 ˜5×10 13 /cm 2 when the first and second transistors are PMOS transistors.
Claim 11
Dependent Claim
13 words
The method according to claim 9 , wherein the impurity ions include arsenic.
Claim 12
Dependent Claim
40 words
The method according to claim 2 , wherein the impurity ions include BF2 or In when the first and second transistors are NMOS transistors and wherein the impurity ions include Sb when the first and second transistors are PMOS transistors.
Claim 13
Dependent Claim
26 words
The method according to claim 1 , further comprising the step of forming third insulating layers at both sides of the first and second gate electrodes.
Claim 14
Dependent Claim
33 words
The method according to claim 1 , further comprising the step of forming a lightly doped drain (LDD) region in the semiconductor substrate at both sides of the first and second gate electrodes.
Claim 15
Dependent Claim
42 words
The method according to claim 13 , further comprising the step of forming a halo region in the semiconductor substrate at both sides of the first and second gate electrodes, wherein the halo region has a depth greater than the LDD region.
Claim 16
Dependent Claim
45 words
The method according to claim 14 , wherein the halo region is formed by implanting BF 2 ions using an energy of 100˜160 KeV, a dosage of 1×10 13 ˜1×10 14 /cm 2 and a tilted angle of 0˜30° when the transistors are NMOS transistors.
Claim 17
Dependent Claim
48 words
The method according to claim 14 , wherein the halo region is formed by implanting phosphorus ions using an energy of 60˜140 KeV, a dosage of 1×10 13 ˜1×10 14 /cm 2 , and a tilted angle of 0˜30° when the first and second transistors are PMOS transistors.
Claim 18
Dependent Claim
28 words
The method according to claim 14 , wherein the halo region is formed by implanting boron or indium ions when the first and second transistors are NMOS transistors.
Claim 19
Dependent Claim
24 words
The method according to claim 14 , wherein the halo region is formed by implanting As or Sb when the transistors are a PMOS.
Claim 20
Dependent Claim
23 words
The method according to claim 1 , wherein the first and second transistors have the same threshold value and a different gamma value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |