Method of fabricating deep submicron MOSFET with narrow gate length using thermal oxidation of polysilicon

Claim 1

A method of forming a gate for a MOS transistor on a semiconductor substrate, said method comprising the steps of: forming a gate oxide layer on said semiconductor substrate; forming a first polysilicon layer on said gate oxide layer; forming a dielectric layer on said first polysilicon layer for isolating said first polysilicon layer; forming a second polysilicon layer on said dielectric layer; etching said second polysilicon layer to form an opening in said second polysilicon layer; oxidizing said second polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to said second polysilicon layer thereby narrowing said opening; performing a local threshold voltage implant by using said polysilicon-oxide layer as an ion implant mask to dope ions into said substrate; forming a metal in said opening; removing said polysilicon-oxide layer; removing said dielectric layer; and patterning and etching said first polysilicon layer to form a gate of said MOS.

Claim 2

A method of forming a gate for a MOS transistor on a semiconductor substrate, said method comprising the steps of: forming a gate oxide layer on said semiconductor substrate; forming a first polysilicon layer on said gate oxide layer; forming a dielectric layer on said first polysilicon layer for isolating said first polysilicon layer; forming a second polysilicon layer on said dielectric layer; etching said second polysilicon layer to form an opening in said second polysilicon layer; oxidizing said second polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to said second polysilicon layer thereby narrowing said opening; performing a local threshold voltage implant by using said polysilicon-oxide layer as an ion implant mask to dope ions into said substrate; forming a metal in said opening; removing said polysilicon-oxide layer; removing said dielectric layer; and patterning and etching said first polysilicon layer to form a gate of said MOS.

Claim 6

The method of claim, 4 wherein said nitride layer is formed to have a thickness of approximately 300-1000 angstroms.

Claim 15

A method for forming a gate for a MOS transistor on a semiconductor substrate, the method comprising the steps of: forming a gate oxide on said semiconductor substrate; forming a first polysilicon layer atop said gate oxide; forming an etching isolation layer atop said first polysilicon layer; forming a second polysilicon layer atop said etching isolation layer; forming an opening in said second polysilicon layer down to said etching isolation layer; thermally oxidizing said second polysilicon layer into a polysilicon-oxide layer and to narrow said opening; removing said etching isolation layer in said opening; and forming a metal contact atop said first polysilicon layer in said opening; etching away said polysilicon-oxide layer, said remaining etching isolation layer, said first polysilicon layer, and said gate oxide not covered by said metal contact.

Claim 16

A method for forming a gate for a MOS transistor on a semiconductor substrate, the method comprising the steps of: forming a gate oxide on said semiconductor substrate; forming a first polysilicon layer atop said gate oxide; forming an etching isolation layer atop said first polysilicon layer; forming a second polysilicon layer atop said etching isolation layer; forming an opening in said second polysilicon layer down to said etching isolation layer; thermally oxidizing said second polysilicon layer into a polysilicon-oxide layer and to narrow said opening; removing said etching isolation layer in said opening; and forming a metal contact atop said first polysilicon layer in said opening; etching away said polysilicon-oxide layer, said remaining etching isolation layer, said first polysilicon layer, and said gate oxide not covered by said metal contact.