US5484743A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned anti-punchthrough implantation process
Assignee: United Microelectronics Corp
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Filing: 1995-02-27
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Granted: 1996-01-16
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Expires: 2015-02-27
Abstract
Abstract The invention relates to a method of forming an improved MOSFET device structure for use in ultra large scale integration devices. A local self-aligned anti-punchthrough region is formed directly under the gate electrode using ion implantation. The local anti-punchthrough region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local anti-punchthrough region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. Channel mobility is not degraded and the source and drain junction capacitances are reduced. The invention can be used in either N channel or P channel MOSFET devices, and in either LDD (light doped drain) or non-LDD devices.
Inventors
- 👤 Joe Ko
- 👤 Chen-Chiu Hsue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:03
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D30/0217; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D30/60; H10D30/601
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
222 words
A method for forming a local anti-punchthrough region, comprising the steps of: providing a silicon substrate having a threshold voltage adjustment concentration formed by ion implantation; forming a gate oxide layer on the surface of said silicon substrate; forming a polysilicon layer on the surface of said gate oxide layer; forming a nitride layer on the surface of said polysilicon layer; etching a gate electrode opening with sidewalls in said nitride layer; forming a first oxide spacer on said sidewalls of said gate electrode opening; forming said local anti-punchthrough region in said silicon substrate directly below said gate electrode opening by means of ion implantation through said gate electrode opening having said first oxide spacer on said sidewalls of said gate electrode opening; removing said first oxide spacer; forming a layer of polyoxide on that part of the polysilicon layer directly below said gate electrode opening; etching away said nitride layer; forming a polysilicon gate electrode with sidewalls by etching away that part of said polysilicon layer not covered by said layer of polyoxide using said layer of polyoxide as a mask; forming a second oxide spacer on said sidewalls of said polysilicon gate electrode; forming a light doped drain source/drain region in said silicon substrate directly below said second oxide spacer; and forming a main source/drain region in said silicon substrate.
Claim 2
Independent Claim
222 words
A method for forming a local anti-punchthrough region, comprising the steps of: providing a silicon substrate having a threshold voltage adjustment concentration formed by ion implantation; forming a gate oxide layer on the surface of said silicon substrate; forming a polysilicon layer on the surface of said gate oxide layer; forming a nitride layer on the surface of said polysilicon layer; etching a gate electrode opening with sidewalls in said nitride layer; forming a first oxide spacer on said sidewalls of said gate electrode opening; forming said local anti-punchthrough region in said silicon substrate directly below said gate electrode opening by means of ion implantation through said gate electrode opening having said first oxide spacer on said sidewalls of said gate electrode opening; removing said first oxide spacer; forming a layer of polyoxide on that part of the polysilicon layer directly below said gate electrode opening; etching away said nitride layer; forming a polysilicon gate electrode with sidewalls by etching away that part of said polysilicon layer not covered by said layer of polyoxide using said layer of polyoxide as a mask; forming a second oxide spacer on said sidewalls of said polysilicon gate electrode; forming a light doped drain source/drain region in said silicon substrate directly below said second oxide spacer; and forming a main source/drain region in said silicon substrate.
Claim 3
Dependent Claim
24 words
The method of claim 1 wherein said silicon substrate is P - type silicon and said local anti-punchthrough region is P - type silicon.
Claim 4
Dependent Claim
34 words
The method of claim 2 wherein said local anti-punchthrough region is formed using a boron ion beam of between about 5×10 12 and 1.5×10 13 ions/cm 2 at between about 50 and 200 keV.
Claim 5
Dependent Claim
24 words
The method of claim 1 wherein said silicon substrate is N - type silicon and said local anti-punchthrough region is N - type silicon.
Claim 6
Dependent Claim
34 words
The method of claim 4 wherein said local anti-punchthrough region is formed using a phosphorous ion beam of between about 1×10 12 and 1×10 13 ions/cm 2 at between about 100 and 250 keV.
Claim 7
Dependent Claim
35 words
The method of claim 1 wherein said silicon substrate is P - type silicon, said main source/drain region is N + type silicon, and said light doped drain source/drain region is N - type silicon.
Claim 8
Dependent Claim
35 words
The method of claim 1 wherein said silicon substrate is N - type silicon, said main source/drain region is P + type silicon, and said light doped drain source/drain region is P - type silicon.
Claim 9
Independent Claim
224 words
A method for forming a local anti-punchthrough region, comprising the steps of: providing a silicon substrate having a threshold voltage adjustment concentration formed by ion implantation; forming a gate oxide layer on the surface of said silicon substrate; forming a polysilicon layer on the surface of said gate oxide layer; forming a nitride layer on the surface of said polysilicon layer; etching a gate electrode opening with sidewalls in said nitride layer; forming a first oxide spacer on said sidewalls of said gate electrode opening; forming said local anti-punchthrough region in said silicon substrate directly below said gate electrode opening by means of ion implantation through said gate electrode opening having said first oxide spacer on said sidewalls of said gate electrode opening; removing said first oxide spacer; forming a layer of TiSi 2 on that part of the polysilicon layer directly below said gate electrode opening; etching away said nitride layer; forming a polysilicon gates electrode with sidewalls by etching away that part of said polysilicon layer not covered by said layer of TiSi 2 using said layer TiSi 2 as a mask; forming a second oxide spacer on said sidewalls of said polysilicon gate electrode; forming a light doped drain source/drain region in said silicon substrate directly below said second oxide spacer; and forming a main source/drain region in said silicon substrate.
Claim 10
Independent Claim
224 words
A method for forming a local anti-punchthrough region, comprising the steps of: providing a silicon substrate having a threshold voltage adjustment concentration formed by ion implantation; forming a gate oxide layer on the surface of said silicon substrate; forming a polysilicon layer on the surface of said gate oxide layer; forming a nitride layer on the surface of said polysilicon layer; etching a gate electrode opening with sidewalls in said nitride layer; forming a first oxide spacer on said sidewalls of said gate electrode opening; forming said local anti-punchthrough region in said silicon substrate directly below said gate electrode opening by means of ion implantation through said gate electrode opening having said first oxide spacer on said sidewalls of said gate electrode opening; removing said first oxide spacer; forming a layer of TiSi 2 on that part of the polysilicon layer directly below said gate electrode opening; etching away said nitride layer; forming a polysilicon gates electrode with sidewalls by etching away that part of said polysilicon layer not covered by said layer of TiSi 2 using said layer TiSi 2 as a mask; forming a second oxide spacer on said sidewalls of said polysilicon gate electrode; forming a light doped drain source/drain region in said silicon substrate directly below said second oxide spacer; and forming a main source/drain region in said silicon substrate.
Claim 11
Dependent Claim
24 words
The method of claim 8 wherein said silicon substrate is P - type silicon and said local anti-punchthrough region is P - type silicon.
Claim 12
Dependent Claim
34 words
The method of claim 9 wherein said local anti-punchthrough region is formed using a boron ion beam of between about 5×10 12 and 1.5×10 13 ions/cm 2 at between about 50 and 200 keV.
Claim 13
Dependent Claim
24 words
The method of claim 8 wherein said silicon substrate is N - type silicon and said local anti-punchthrough region is N - type silicon.
Claim 14
Dependent Claim
34 words
The method of claim 11 wherein said local anti-punchthrough region is formed using a phosphorous ion beam of between about 1×10 12 and 1×10 13 ions/cm 2 at between about 100 and 250 keV.
Claim 15
Dependent Claim
35 words
The method of claim 8 wherein said silicon substrate is P - type silicon, said main source/drain region is N + type silicon, and said light doped drain source/drain region is N - type silicon.
Claim 16
Dependent Claim
35 words
The method of claim 8 wherein said silicon substrate is N - type silicon, said main source/drain region is P + type silicon, and said light doped drain source/drain region is P - type silicon.
Claim 17
Dependent Claim
29 words
The method of claim 8 wherein said layer of TiSi 2 is formed by sputtering a layer of titanium on said silicon substrate followed by rapid thermal process annealing.
Claim 18
Dependent Claim
18 words
The method of claim 15 wherein said layer of titanium is between about 200 and 500 Angstroms thick.
Claim 19
Dependent Claim
55 words
The method of claim 15 wherein said rapid thermal process annealing is carried out at temperatures of between about 600° C. and 700° C. for between about 10 seconds and 100 seconds in nitrogen followed by temperatures of between about 700° C. and 900° C. for between about 10 seconds and 100 seconds in nitrogen.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |