Method for fabricating MOS device with reduced anti-punchthrough region

Claim 1

A method for fabricating MOS device, comprising the steps of: providing a semiconductor substrate of a first conductivity type which has a device isolation layer formed thereon; sequentially forming a first conducting layer and a barrier layer on said semiconductor substrate; patterning said barrier layer to form an opening; forming first sidewall spacers on the sidewalls of said barrier layer; etching a portion of said first conducting layer not covered by said barrier layer and said first sidewall spacer to expose an area of said semiconductor substrate which will subsequently define a gate region; forming second sidewall spacers on sidewalls of said first sidewall spacers and on said first conducting layer; implanting impurities of the first conductivity type through an opening defined between said second sidewall spacers and into said semiconductor substrate to form an anti-punchthrough region therein; forming a gate oxide layer on the surface of said semiconductor substrate between said second sidewall spacers; forming a second conducting layer overlying said barrier layer, said first sidewall spacer, said second sidewall spacer, and said gate oxide layer; etching a portion of said second conducting layer over said barrier layer, whereby the remaining portion of said second conducting layer within said opening forms a gate; removing said barrier layer; implanting impurities of a second conductivity type into said first conducting layer and said gate, wherein said impurities of the second conductivity type diffuse into said semiconductor substrate to form both heavily doped source/drain regions under said first conducting layer and lightly doped source/drain regions under said second sidewall spacers simultaneously; forming a dielectric layer overlying the whole surface of said semiconductor substrate; and forming metal contacts in said dielectric layer.

Claim 2

A method for fabricating MOS device, comprising the steps of: providing a semiconductor substrate of a first conductivity type which has a device isolation layer formed thereon; sequentially forming a first conducting layer and a barrier layer on said semiconductor substrate; patterning said barrier layer to form an opening; forming first sidewall spacers on the sidewalls of said barrier layer; etching a portion of said first conducting layer not covered by said barrier layer and said first sidewall spacer to expose an area of said semiconductor substrate which will subsequently define a gate region; forming second sidewall spacers on sidewalls of said first sidewall spacers and on said first conducting layer; implanting impurities of the first conductivity type through an opening defined between said second sidewall spacers and into said semiconductor substrate to form an anti-punchthrough region therein; forming a gate oxide layer on the surface of said semiconductor substrate between said second sidewall spacers; forming a second conducting layer overlying said barrier layer, said first sidewall spacer, said second sidewall spacer, and said gate oxide layer; etching a portion of said second conducting layer over said barrier layer, whereby the remaining portion of said second conducting layer within said opening forms a gate; removing said barrier layer; implanting impurities of a second conductivity type into said first conducting layer and said gate, wherein said impurities of the second conductivity type diffuse into said semiconductor substrate to form both heavily doped source/drain regions under said first conducting layer and lightly doped source/drain regions under said second sidewall spacers simultaneously; forming a dielectric layer overlying the whole surface of said semiconductor substrate; and forming metal contacts in said dielectric layer.