US5270232A
Expired / Lapsed
US
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Process for fabricating field effect transistor
Assignee: Hitachi Ltd
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Filing: 1992-09-10
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Granted: 1993-12-14
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Expires: 2012-09-10
Abstract
Abstract A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.
Inventors
- 👤 Shinichiro Kimura
- 👤 Shoji Shukuri
- 👤 Hiromasa Noda
- 👤 Digh Hisamoto
- 👤 Hideyuki Matsuoka
- 👤 Kazuyoshi Torii
- 👤 Natsuki Yokoyama
- 👤 Toshiyuki Yoshimura
- 👤 Kazunori Tsujimoto
- 👤 Eiji Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0273; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D64/021; H10D64/025; H10D64/027; H10P; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
238 words
A process for fabricating an MOS type field effect transistor comprising: a step of forming a first insulator film on a semiconductor substrate, and then a first conductor layer on said first insulator film; a step of forming an opening in said first conductor layer and said first insulator film, and forming a second conductor layer on the sidewall of said opening, said second conductor layer containing impurities of a predetermined conduction type ; a step of forming a second insulator film to cover therewith both said second conductor layer on said sidewall of said opening and the substrate surface at said opening; a step of forming a third conductor layer on the sidewall of said second insulator film at said opening, said third conductor layer containing impurities of said predetermined conduction type; a step of diffusing the impurities of said predetermined conduction type from said second conductor layer and said third conductor layer into said semiconductor substrate so as to form a source region and a drain region of the MOS transistor; a step of removing said third conductor layer and said second insulator film after formation of said source and drain regions, and forming a third insulator film on the sidewall of said second conductor layer thus exposed; and a step of forming a fourth insulator film as a gate insulator film on the semiconductor substrate surface in an area bounded by said third insulator film.
Claim 2
Dependent Claim
238 words
A process for fabricating an MOS type field effect transistor comprising: a step of forming a first insulator film on a semiconductor substrate, and then a first conductor layer on said first insulator film; a step of forming an opening in said first conductor layer and said first insulator film, and forming a second conductor layer on the sidewall of said opening, said second conductor layer containing impurities of a predetermined conduction type ; a step of forming a second insulator film to cover therewith both said second conductor layer on said sidewall of said opening and the substrate surface at said opening; a step of forming a third conductor layer on the sidewall of said second insulator film at said opening, said third conductor layer containing impurities of said predetermined conduction type; a step of diffusing the impurities of said predetermined conduction type from said second conductor layer and said third conductor layer into said semiconductor substrate so as to form a source region and a drain region of the MOS transistor; a step of removing said third conductor layer and said second insulator film after formation of said source and drain regions, and forming a third insulator film on the sidewall of said second conductor layer thus exposed; and a step of forming a fourth insulator film as a gate insulator film on the semiconductor substrate surface in an area bounded by said third insulator film.
Claim 3
Dependent Claim
20 words
The process according to claim 1, wherein the thickness of said second insulator film is about 10 to 20 Å.
Claim 4
Dependent Claim
27 words
The process according to claim 1, wherein said second insulator film is formed by oxidation of said second conductor layer and the substrate surface at said opening.
Claim 5
Dependent Claim
36 words
The process according to claim I, wherein said second conductor film is formed on the lower side of a fourth insulator film provided with an opening smaller than said opening formed in said first insulator film.
Claim 6
Dependent Claim
13 words
The process according to claim 1, wherein said second conductor film comprises polysilicon.
Claim 7
Dependent Claim
16 words
The process according to claim 1, wherein said fist insulator film comprises a silicon nitride film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |