Having halo regions integrated circuit device structure

Claim 2

A field effect transistor for an integrated circuit device, comprising: a substrate region having a first conductivity type; a gate electrode over said substrate region; lightly doped drain regions in said substrate region adjacent said gate electrode, said lightly doped drain regions having a second conductivity type; heavily doped source/drain regions having the second conductivity type in said substrate region adjacent said lightly doped drain regions; and halo regions having the first conductivity type within said substrate region adjacent said gate electrode and extending a relatively short distance into said source/drain regions, wherein those portions of said source/drain regions which are spaced further from said gate electrode than the relatively short distance do not contain the first conductivity type dopant used to form the halo regions.

Claim 3

The structure of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

Claim 4

The structure of claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

Claim 5

The structure of claim 1, further comprising: a threshold adjust implant region within the substrate region under said gate electrode and extending laterally therefrom, said threshold adjust implant region having a lateral extent approximately coincident with said halo regions.

Claim 6

The structure of claim 1, further comprising a second substrate region having the second conductivity type; a second gate electrode over said second substrate region; lightly doped drain regions in said second substrate region adjacent said second gate electrode, said lightly doped drain regions having the first conductivity type; heavily doped source/drain regions having the first conductivity type in said second substrate region adjacent said lightly doped drain regions; and halo regions having the second conductivity type within said second substrate region adjacent said second gate electrode and extending a second relatively short distance into said source/drain regions, wherein those portions of said source/drain regions which are spaced further from said second gate electrode than the second relatively short distance do not contain the second conductivity type dopant used to form the halo regions.

Claim 7

An integrated circuit device, comprising: a substrate having a region of monolithic semiconductor material near a first surface thereof; a conductive gate electrode capacitively coupled to said semiconductor material near said first surface, to define a channel region therein; a source region and a drain region within said semiconductor material, both doped with a first conductivity type; said source and drain regions being separated by said channel region, such that the voltage of said gate will control inversion of said channel region to selectably block conduction between said source and drain regions; wherein portions of said source and drain regions closest to said gate electrode have a diffusion profile corresponding to the overlaid combination of a first diffusion of said first conductivity type, which provides the majority of the doping of said source and drain regions; a second diffusion, of said first conductivity type, which has a longer lateral diffusion length toward said gate than does said first diffusion, and a third diffusion, of a second conductivity type, which has a longer lateral diffusion length toward said gate than does said first diffusion, and which has a greater depth than said second diffusion; and wherein other portions of said source and drain regions have a diffusion profile which includes said first diffusion but NOT said third diffusion.

Claim 8

An integrated circuit device, comprising: a substrate having a region of monolithic semiconductor material near a first surface thereof; a conductive gate electrode capacitively coupled to said semiconductor material near said first surface, to define a channel region therein; a source region and a drain region within said semiconductor material, both doped with a first conductivity type; said source and drain regions being separated by said channel region, such that the voltage of said gate will control inversion of said channel region to selectably block conduction between said source and drain regions; wherein portions of said source and drain regions closest to said gate electrode have a diffusion profile corresponding to the overlaid combination of a first diffusion of said first conductivity type, which provides the majority of the doping of said source and drain regions; a second diffusion, of said first conductivity type, which has a longer lateral diffusion length toward said gate than does said first diffusion, and a third diffusion, of a second conductivity type, which has a longer lateral diffusion length toward said gate than does said first diffusion, and which has a greater depth than said second diffusion; and wherein other portions of said source and drain regions have a diffusion profile which includes said first diffusion but NOT said third diffusion.

Claim 9

The integrated circuit device of claim 6, wherein said first conductivity type is N-type.

Claim 10

The integrated circuit device of claim 6, wherein said first and second diffusions comprise two different dopant species.

Claim 11

The integrated circuit device of claim 6, wherein said second diffusion comprises phosphorus, and said first diffusion comprises arsenic.

Claim 12

The integrated circuit device of claim 6, wherein said second diffusion comprises phosphorus, and said first diffusion comprises arsenic.

Claim 13

The integrated circuit device of claim 6, wherein said gate is separated from said channel by a thin layer of silicon dioxide.

Claim 14

The integrated circuit device of claim 6, wherein said channel region, where not abutted by said source and drain, is abutted by an isolation region.

Claim 15

The integrated circuit device of claim 6, wherein said gate electrode predominantly comprises polysilicon.

Claim 16

An integrated circuit device, comprising: a substrate having a region of monolithic semiconductor material near a first surface thereof; a conductive gate electrode capacitively coupled to said semiconductor material near said first surface, to define a channel region therein; a source region and a drain region within said semiconductor material, both doped with a first conductivity type; said source and drain regions being separated by said channel region, such that the voltage of said gate will control inversion of said channel region to selectably block conduction between said source and drain regions; wherein portions of said source and drain regions closest to said gate electrode have a diffusion profile corresponding to the overlaid combination of a first diffusion of said first conductivity type, which provides the majority of the doping of said source and drain regions; a second diffusion, of said first conductivity type, which has a longer lateral diffusion length toward said gate than does said first diffusion, and a third diffusion, of a second conductivity type, which has a longer lateral diffusion length toward said gate than does said first diffusion, and which has a greater depth than said second diffusion; and wherein other portions of said source and drain regions have a diffusion profile which includes said first diffusion but NOT said second diffusion nor said third diffusion.

Claim 17

An integrated circuit device, comprising: a substrate having a region of monolithic semiconductor material near a first surface thereof; a conductive gate electrode capacitively coupled to said semiconductor material near said first surface, to define a channel region therein; a source region and a drain region within said semiconductor material, both doped with a first conductivity type; said source and drain regions being separated by said channel region, such that the voltage of said gate will control inversion of said channel region to selectably block conduction between said source and drain regions; wherein portions of said source and drain regions closest to said gate electrode have a diffusion profile corresponding to the overlaid combination of a first diffusion of said first conductivity type, which provides the majority of the doping of said source and drain regions; a second diffusion, of said first conductivity type, which has a longer lateral diffusion length toward said gate than does said first diffusion, and a third diffusion, of a second conductivity type, which has a longer lateral diffusion length toward said gate than does said first diffusion, and which has a greater depth than said second diffusion; and wherein other portions of said source and drain regions have a diffusion profile which includes said first diffusion but NOT said second diffusion nor said third diffusion.

Claim 18

The integrated circuit device of claim 14, wherein said first conductivity type is N-type.

Claim 19

The integrated circuit device of claim 14, wherein said first and second diffusions comprise two different dopant species.

Claim 20

The integrated circuit device of claim 14, wherein said second diffusion comprises phosphorus, and said first diffusion comprises arsenic.

Claim 21

The integrated circuit device of claim 14, wherein said second diffusion comprises phosphorus, and said first diffusion comprises arsenic.

Claim 22

The integrated circuit device of claim 14, wherein said gate is separated from said channel by a thin layer of silicon dioxide.

Claim 23

The integrated circuit device of claim 14, wherein said channel region, where not abutted by said source and drain, is abutted by an isolation region.

Claim 24

The integrated circuit device of claim 14, wherein said gate electrode predominantly comprises polysilicon.