Method for forming MOS transistors

Claim 1

A method of implanting a diffusion region of a MOS transistor as the transistor is being formed on a supporting substrate, comprising the following steps: patterning and etching a gate by sequential application of a resist, followed by an anisotropic etch and an isotropic etch to produce a resist overhang covering one edge of the gate; implanting a dopant to produce a first diffusion region located within an area of the substrate adjacent to the gate and partially defined by the resist overhang covering the one edge of the gate; isotropically etching the remaining resist on the gate to eliminate overhang while retaining the resist over the gate; and implanting additional dopant to product a halo diffusion region within an area of the substrate that surrounds the first diffusion region and has a border partially defined by the one edge of the gate.

Claim 2

A method of implanting a diffusion region of a MOS transistor as the transistor is being formed on a supporting substrate, comprising the following steps: patterning and etching a gate by sequential application of a resist, followed by an anisotropic etch and an isotropic etch to produce a resist overhang covering one edge of the gate; implanting a dopant to produce a first diffusion region located within an area of the substrate adjacent to the gate and partially defined by the resist overhang covering the one edge of the gate; isotropically etching the remaining resist on the gate to eliminate overhang while retaining the resist over the gate; and implanting additional dopant to product a halo diffusion region within an area of the substrate that surrounds the first diffusion region and has a border partially defined by the one edge of the gate.

Claim 6

A method of implanting a diffusion region of a MOS transistor as the transistor is being formed on a supporting substrate, comprising the following steps: applying resist to exposed surfaces of a layer of polysilicon deposited over a thin layer of silicon dioxide on the substrate; patterning and etching a gate in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce a resist overhang; implanting a dopant to produce a first diffusion region located within an area of the substrate adjacent to the gate and partially defined by the resist overhang; isotropically etching the resist to eliminate overhang while retaining the resist over the gate; and implanting additional dopant to produce a halo diffusion region within an area of the substrate that surrounds the first diffusion region and has a border partially defined by the one edge of the gate.

Claim 7

A method of implanting a diffusion region of a MOS transistor as the transistor is being formed on a supporting substrate, comprising the following steps: applying resist to exposed surfaces of a layer of polysilicon deposited over a thin layer of silicon dioxide on the substrate; patterning and etching a gate in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce a resist overhang; implanting a dopant to produce a first diffusion region located within an area of the substrate adjacent to the gate and partially defined by the resist overhang; isotropically etching the resist to eliminate overhang while retaining the resist over the gate; and implanting additional dopant to produce a halo diffusion region within an area of the substrate that surrounds the first diffusion region and has a border partially defined by the one edge of the gate.

Claim 11

A method of implanting diffusion regions of MOS transistors during their production by use of split-poly techniques in which differing transistors are processed separately, comprising the following steps: applying a layer of polysilicon over a thin layer of silicon dioxide to a supporting substrate; applying a blanket layer of resist to exposed surfaces of the polysilicon and substrate; patterning and etching a gate in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce resist overhangs covering the edges of the gate and the remaining areas about the layer of polysilicon; implanting a dopant to produce first diffusion regions located within an area of the substrate adjacent to the gate and partially defined by the resist overhang covering the edges of the gate; isotropically etching the resist to eliminate overhang while retaining the resist over both the gate and the remaining layer of polysilicon; and implanting additional dopant to produce halo diffusion regions within areas of the substrate that surround the first diffusion regions and having borders partially defined by the edges of the gate.

Claim 12

A method of implanting diffusion regions of MOS transistors during their production by use of split-poly techniques in which differing transistors are processed separately, comprising the following steps: applying a layer of polysilicon over a thin layer of silicon dioxide to a supporting substrate; applying a blanket layer of resist to exposed surfaces of the polysilicon and substrate; patterning and etching a gate in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce resist overhangs covering the edges of the gate and the remaining areas about the layer of polysilicon; implanting a dopant to produce first diffusion regions located within an area of the substrate adjacent to the gate and partially defined by the resist overhang covering the edges of the gate; isotropically etching the resist to eliminate overhang while retaining the resist over both the gate and the remaining layer of polysilicon; and implanting additional dopant to produce halo diffusion regions within areas of the substrate that surround the first diffusion regions and having borders partially defined by the edges of the gate.

Claim 16

A method of implanting diffusion regions of a CMOS transistor as the transistor is being formed by use of split-poly techniques in which a complementary transistor having a gate produced from a layer of polysilicon and adjacent diffusion regions is first formed on a common substrate, comprising the following steps: applying a blanket layer of resist covering the first-formed transistor and the exposed surfaces of the layer of polysilicon on top of a thin layer of silicon dioxide between the polysilicon and substrate; patterning and etching a transistor gate in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce resist overhangs; implanting a dopant to produce first diffusion regions on the substrate that are located within areas adjacent to the transistor gate under formation and partially defined by the resist overhang; isotropically etching the resist to eliminate overhang while retaining the resist over the transistor gate; and implanting additional dopant to produce halo diffusion regions within areas of the substrate that surround the first diffusion regions and having borders partially defined by edges of the gate.

Claim 17

A method of implanting diffusion regions of a CMOS transistor as the transistor is being formed by use of split-poly techniques in which a complementary transistor having a gate produced from a layer of polysilicon and adjacent diffusion regions is first formed on a common substrate, comprising the following steps: applying a blanket layer of resist covering the first-formed transistor and the exposed surfaces of the layer of polysilicon on top of a thin layer of silicon dioxide between the polysilicon and substrate; patterning and etching a transistor gate in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce resist overhangs; implanting a dopant to produce first diffusion regions on the substrate that are located within areas adjacent to the transistor gate under formation and partially defined by the resist overhang; isotropically etching the resist to eliminate overhang while retaining the resist over the transistor gate; and implanting additional dopant to produce halo diffusion regions within areas of the substrate that surround the first diffusion regions and having borders partially defined by edges of the gate.

Claim 21

A method of implanting diffusion regions of a CMOS transistor using split-poly techniques in which complementary transistors are processed separately, comprising the following steps: applying a layer of polysilicon over a thin silicon dioxide layer on a supporting substrate; applying a blanket layer of resist to the layer of polysilicon; patterning and etching a gate for a first transistor in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce resist overhangs covering the gate of the first transistor and the remaining areas about the layer of polysilicon; implanting a dopant to produce first diffusion regions on the substrate that are located within areas adjacent to the gate of the first transistor and are partially defined by the resist overhang; isotropically etching the resist to eliminate overhang while continuing to cover both the gate of the first transistor and the remaining areas about the layer of polysilicon; implanting additional dopant to produce halo diffusion regions within areas of the substrate that surround the first diffusion regions and having borders partially defined by edges of the gate of the first transistor to complete its formation; reestablishing a blanket layer of resist; patterning and etching a gate of a second transistor in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce resist overhangs covering the gate of the second transistor; implanting a dopant to produce second diffusion regions on the substrate that are located within areas adjacent to the gate of the second transistor and partially defined by the resist overhang; isotropically etching the resist to eliminate overhang while retaining the resist over the gate and the first transistor; and implanting additional dopant to produce halo diffusion regions within areas of the substrate that surround the second diffusion regions and having borders partially defined by edges of the second gate to complete formation of the second transistor of the complementary pair.

Claim 22

A method of implanting diffusion regions of a CMOS transistor using split-poly techniques in which complementary transistors are processed separately, comprising the following steps: applying a layer of polysilicon over a thin silicon dioxide layer on a supporting substrate; applying a blanket layer of resist to the layer of polysilicon; patterning and etching a gate for a first transistor in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce resist overhangs covering the gate of the first transistor and the remaining areas about the layer of polysilicon; implanting a dopant to produce first diffusion regions on the substrate that are located within areas adjacent to the gate of the first transistor and are partially defined by the resist overhang; isotropically etching the resist to eliminate overhang while continuing to cover both the gate of the first transistor and the remaining areas about the layer of polysilicon; implanting additional dopant to produce halo diffusion regions within areas of the substrate that surround the first diffusion regions and having borders partially defined by edges of the gate of the first transistor to complete its formation; reestablishing a blanket layer of resist; patterning and etching a gate of a second transistor in the layer of polysilicon by sequentially applying an anisotropic etch and an isotropic etch to produce resist overhangs covering the gate of the second transistor; implanting a dopant to produce second diffusion regions on the substrate that are located within areas adjacent to the gate of the second transistor and partially defined by the resist overhang; isotropically etching the resist to eliminate overhang while retaining the resist over the gate and the first transistor; and implanting additional dopant to produce halo diffusion regions within areas of the substrate that surround the second diffusion regions and having borders partially defined by edges of the second gate to complete formation of the second transistor of the complementary pair.