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JPS59201415A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Toshiba Corp
•
Filing: 1983-04-28
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Granted: —
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Expires: 2003-04-28
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Abstract

Abstract PURPOSE:To obtain super-fine gate electrode width by forming the source and drain by ion implantation after providing a resist mask and etching the gate electrode material, and then executing shallow ion implantation from the resist with the narrow gate electrode used as the mask. CONSTITUTION:A resist mask 45 is formed on a poly-Si 44 on an oxide thin film 43 of a Si substrate 41 and then it is etched. Thereby, width of layer 44 is made narrower than that of mask 45 and the source layer 46 and drain layer 47 are formed by ion implantation. With the poly-Si layer 44 used as the mask, shallower ion implantation is carried out in order to form the regions 461, 471 in the channel side. The regions 461, 471 less spread in lateral and elongation of deletion layers 61, 62 is also small and therefore short channel effect can be neglected. According to this structure, an MOSFET of super fine gate width where the short channel effect can be neglected can be obtained stably with each control for threshold level.

Inventors

  • 👤 Yukihiro Saeki
  • 👤 佐伯 幸弘

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 10:27
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20

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