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US6146985A
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Low capacitance interconnection
Assignee: Advanced Micro Devices Inc
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Filing: 1998-05-04
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Granted: 2000-11-14
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Expires: 2018-05-04
Abstract
Abstract A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.
Inventors
- 👤 Donald L. Wollesen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:33
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; H10W20/45; H10W20/48; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W72/59; H10W72/90; H10W72/931; H10W72/934; H10W72/951; H10W72/952; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
118 words
A method of manufacturing a semiconductor device, which method comprises sequentially: depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern; removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; and depositing a first conformal dielectric coating thereon, wherein each dielectric layer comprises air spaces between and adjoining each portion of the first dielectric material having the first conformal dielectric coating thereon and each conductive level comprises a plurality of conductive patterns separated by air spaces.
Claim 2
Independent Claim
118 words
A method of manufacturing a semiconductor device, which method comprises sequentially: depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern; removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; and depositing a first conformal dielectric coating thereon, wherein each dielectric layer comprises air spaces between and adjoining each portion of the first dielectric material having the first conformal dielectric coating thereon and each conductive level comprises a plurality of conductive patterns separated by air spaces.
Claim 3
Dependent Claim
20 words
The method according to claim 1, wherein the first dielectric material is a silicon oxide, silicon nitride or silicon oxynitride.
Claim 4
Dependent Claim
21 words
The method according to claim 1, wherein the conformal dielectric coating comprises a silicon oxide, silicon nitride or a silicon oxynitride.
Claim 5
Dependent Claim
42 words
The method according to claim 1, further comprising: forming a plurality of vias electrically connecting conductive patterns of conductive layers; and forming a contact electrically connecting a conductive pattern of the first conductive layer and each active region in the semiconductor substrate.
Claim 6
Dependent Claim
18 words
The method according to claim 1, wherein the first dielectric material of each dielectric layer is the same.
Claim 7
Dependent Claim
18 words
The method according to claim 1, further comprising depositing a topside dielectric layer on the conformal dielectric coating.
Claim 8
Dependent Claim
16 words
The method according to claim 1, comprising removing sections of each dielectric layer by anisotropic etching.
Claim 9
Dependent Claim
18 words
The method according to claim 6, wherein the topside dielectric layer comprises a polyimide or other organic dielectric.
Claim 10
Dependent Claim
17 words
The method according to claim 6, further comprising forming a thermo-compression ball bond for external electrical contact.
Claim 11
Dependent Claim
18 words
The method according to claim 7, comprising removing sections of each dielectric layer in a single etching stage.
Claim 12
Dependent Claim
18 words
The method according to claim 7, comprising removing sections of each dielectric layer in a single etching stage.
Claim 13
Independent Claim
118 words
A method of manufacturing a semiconductor device, the method comprising sequentially: depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate, wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern; removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; depositing a second dielectric material in each dielectric layer between and adjoining the remaining portions of the first dielectric material; wherein the second dielectric material has a dielectric constant less than the dielectric constant of the first dielectric material and depositing a first conformal dielectric coating.
Claim 14
Independent Claim
118 words
A method of manufacturing a semiconductor device, the method comprising sequentially: depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate, wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern; removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; depositing a second dielectric material in each dielectric layer between and adjoining the remaining portions of the first dielectric material; wherein the second dielectric material has a dielectric constant less than the dielectric constant of the first dielectric material and depositing a first conformal dielectric coating.
Claim 15
Dependent Claim
20 words
The method according to claim 12, wherein the first dielectric material is a silicon oxide, silicon nitride or silicon oxynitride.
Claim 16
Dependent Claim
18 words
The method according to claim 12, wherein the second dielectric material is a polyimide or other organic dielectric.
Claim 17
Dependent Claim
21 words
The method according to claim 12, wherein the conformal dielectric coating comprises a silicon oxide, silicon nitride or a silicon oxynitride.
Claim 18
Dependent Claim
18 words
The method according to claim 12, further comprising depositing a topside dielectric layer on the conformal dielectric coating.
Claim 19
Dependent Claim
18 words
The method according to claim 16, wherein the topside dielectric layer comprises a polyimide or other organic dielectric.
Claim 20
Dependent Claim
42 words
The method according to claim 12, further comprising: forming a plurality of vias electrically connecting conductive patterns of conductive layers; and forming a contact electrically connecting a conductive pattern of the first conductive layer and each active region in the semiconductor substrate.
Claim 21
Dependent Claim
18 words
The method according to claim 12, wherein the first dielectric material of each dielectric layer is the same.
Claim 22
Dependent Claim
16 words
The method according to claim 12, comprising removing sections of each dielectric layer by anisotropic etching.
Claim 23
Dependent Claim
17 words
The method according to claim 16, further comprising forming a thermo-compression ball bond for external electrical contact.
Claim 24
Independent Claim
114 words
A method of manufacturing a semiconductor device, which method comprises sequentially: depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern; removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; depositing a first conformal dielectric coating thereon; and depositing a second conformal dielectric coating on the first conformal dielectric coating; wherein the dielectric constant of the first conformal dielectric coating is less than the dielectric constant of the second conformal dielectric coating.
Claim 25
Independent Claim
114 words
A method of manufacturing a semiconductor device, which method comprises sequentially: depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern; removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; depositing a first conformal dielectric coating thereon; and depositing a second conformal dielectric coating on the first conformal dielectric coating; wherein the dielectric constant of the first conformal dielectric coating is less than the dielectric constant of the second conformal dielectric coating.
Claim 26
Dependent Claim
30 words
The method according to claim 22, wherein the first conformal dielectric coating comprises a polyimide and the second conformal dielectric coating comprises a silicon oxide, silicon nitride or silicon oxynitride.
Claim 27
Independent Claim
148 words
A method of manufacturing a semiconductor device, the method comprising sequentially: depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate, wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern; removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; depositing a second dielectric material in each dielectric layer between and adjoining the remaining portions of the first dielectric material; wherein the second dielectric material has a dielectric constant less than the dielectric constant of the first dielectric material; and depositing a first conformal dielectric coating; and depositing a second conformal dielectric coating thereon; wherein the dielectric constant of the first conformal dielectric coating is less than the dielectric constant of the second conformal dielectric coating.
Claim 28
Independent Claim
148 words
A method of manufacturing a semiconductor device, the method comprising sequentially: depositing a plurality of dielectric and conductive layers sequentially formed on one another above a semiconductor substrate, wherein each dielectric layer comprises a first dielectric material and each conductive layer comprises at least one conductive pattern; removing sections of each dielectric layer leaving only a portion of the first dielectric material substantially under each conductive pattern of the conductive layer thereon; depositing a second dielectric material in each dielectric layer between and adjoining the remaining portions of the first dielectric material; wherein the second dielectric material has a dielectric constant less than the dielectric constant of the first dielectric material; and depositing a first conformal dielectric coating; and depositing a second conformal dielectric coating thereon; wherein the dielectric constant of the first conformal dielectric coating is less than the dielectric constant of the second conformal dielectric coating.
Claim 29
Dependent Claim
30 words
The method according to claim 24, wherein the first conformal dielectric coating comprises a polyimide and the second conformal dielectric coating comprises a silicon oxide, silicon nitride or silicon oxynitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-14 | 2004-05-15 | 2004-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-14 | 2008-05-15 | 2008-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-14 | 2012-05-15 | 2012-11-14 | $7700.00 | Window Closed / Lapsed |