US5598028A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Highly-planar interlayer dielectric thin films in integrated circuits
Assignee: STMicroelectronics SRL
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Filing: 1995-06-06
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Granted: 1997-01-28
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Expires: 2015-06-06
Abstract
Abstract A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the steps of: forming a first barrier layer over a semiconductor substrate wherein integrated devices have been previously obtained; forming a second layer of oxide containing phosphorous and boron over the first undoped oxide the concentration of boron being lower than the concentration of phosphorous; forming a third layer of oxide containing phosphorous and boron over the second oxide layer, the concentration of phosphorous being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer, to obtain a planar surface.
Inventors
- 👤 Aldo Losavio
- 👤 Maurizio Bacchetta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10P; H10P95/00; H10P95/06
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
203 words
An integrated circuit comprising a silicon substrate wherein electronic devices are obtained, comprising first-level electrical interconnection lines over said substrate and second-level electrical interconnection lines, the first-level and second-level electrical interconnection lines being separated by an insulating layer, characterized in that the insulating layer comprises: a barrier layer superimposed over the first-level electrical interconnection lines; a first insulator material layer doped with phosphorous and boron, superimposed over the barrier layer, having a concentration of phosphorous higher than a concentration of boron, the concentration of phosphorous being suitable to make the first insulator material layer act as a gettering layer for high-mobility ions and the concentration of boron depending on the concentration of phosphorous and being suitable to make the first insulator material layer stable; and a generally planar second insulator material layer doped with boron and phosphorous, superimposed over the first insulator material layer, having a concentration of boron in the second insulator material layer equal to or higher than a concentration of phosphorous in the second insulator material layer, the concentration of boron being suitable to lower a melting-point temperature of the second insulator material layer to a prescribed value and the concentration of phosphorous being suitable to make the layer stable.
Claim 2
Dependent Claim
203 words
An integrated circuit comprising a silicon substrate wherein electronic devices are obtained, comprising first-level electrical interconnection lines over said substrate and second-level electrical interconnection lines, the first-level and second-level electrical interconnection lines being separated by an insulating layer, characterized in that the insulating layer comprises: a barrier layer superimposed over the first-level electrical interconnection lines; a first insulator material layer doped with phosphorous and boron, superimposed over the barrier layer, having a concentration of phosphorous higher than a concentration of boron, the concentration of phosphorous being suitable to make the first insulator material layer act as a gettering layer for high-mobility ions and the concentration of boron depending on the concentration of phosphorous and being suitable to make the first insulator material layer stable; and a generally planar second insulator material layer doped with boron and phosphorous, superimposed over the first insulator material layer, having a concentration of boron in the second insulator material layer equal to or higher than a concentration of phosphorous in the second insulator material layer, the concentration of boron being suitable to lower a melting-point temperature of the second insulator material layer to a prescribed value and the concentration of phosphorous being suitable to make the layer stable.
Claim 3
Dependent Claim
27 words
The integrated circuit according to claim 1, characterized in that the concentrations of boron and phosphorous in the second insulator material layer are 4-5% and 4%, respectively.
Claim 4
Dependent Claim
31 words
The integrated circuit according to claim 2, characterized in that the concentrations of phosphorous and boron in the first insulator material layer are higher than 6% and lower than 3%, respectively.
Claim 5
Dependent Claim
91 words
A semiconductor device, comprising: a substrate; first-level electrical interconnections disposed on said substrate; a barrier layer disposed on said interconnections; a first insulator material layer disposed on said barrier layer and including a first concentration of boron and a second concentration of phosphorous greater than said first concentration; a substantially planar second insulator material layer disposed on said first insulator material layer and including a third concentration of boron and a fourth concentration of phosphorous less than said third concentration; and second-level electrical interconnections disposed on said second insulator material layer.
Claim 6
Dependent Claim
91 words
A semiconductor device, comprising: a substrate; first-level electrical interconnections disposed on said substrate; a barrier layer disposed on said interconnections; a first insulator material layer disposed on said barrier layer and including a first concentration of boron and a second concentration of phosphorous greater than said first concentration; a substantially planar second insulator material layer disposed on said first insulator material layer and including a third concentration of boron and a fourth concentration of phosphorous less than said third concentration; and second-level electrical interconnections disposed on said second insulator material layer.
Claim 7
Dependent Claim
32 words
The semiconductor device of claim 4, characterized in that the concentration of phosphorous in the first layer is suitable to make the first layer act as a gettering layer for high-mobility ions.
Claim 8
Dependent Claim
56 words
The semiconductor device of claim 4, characterized in that the substantially planar second layer having a concentration of boron being suitable to lower a melting-point temperature of the second insulator material layer to a prescribed value, and the concentration of phosphorous depending on the concentration of boron and being suitable to have a stable second layer.
Claim 9
Dependent Claim
20 words
The semiconductor device of claim 6, characterized in that the prescribed value is at a temperature of approximately 900° C.
Claim 10
Dependent Claim
24 words
The semiconductor device of claim 4, characterized in that the concentrations of boron and phosphorous in the second layer are 4-5% and 4%, respectively.
Claim 11
Dependent Claim
30 words
The semiconductor device of claim 4, characterized in that the concentrations of phosphorous and boron in the first layer are in the range of 6-9% and lower than 3% respectively.
Claim 12
Dependent Claim
17 words
The semiconductor device of claim 4, characterized in that the barrier layer is a silicon oxide layer.
Claim 13
Dependent Claim
22 words
The semiconductor device of claim 4, characterized in that the barrier layer has a thickness in the range 50 to 300 nm.
Claim 14
Dependent Claim
23 words
The semiconductor device of claim 4, characterized in that the first layer has a thickness in the range 80 nm to 500 nm.
Claim 15
Dependent Claim
17 words
The semiconductor device of claim 4, characterized in that said barrier layer is a silicon nitride layer.
Claim 16
Dependent Claim
17 words
The semiconductor device of claim 4, characterized in that said barrier layer is a silicon oxinitride layer.
Claim 17
Dependent Claim
144 words
A semiconductor device comprising: a) a substrate; b) first-level electrical interconnections disposed on said substrate; c) a barrier layer superimposed over said interconnections; d) a first layer of insulator material containing phosphorous and boron superimposed over said barrier layer, the concentration of boron being lower than 3% and the concentration of phosphorous being in the range of 6-9%, the first insulator material layer being stable and performing a gettering action on high-mobility ions; e) a second layer of insulator material containing phosphorous and boron directly over the first layer of insulator material, the concentration of boron being equal to 4-5% and the concentration of phosphorous being equal to 5%, the second insulator material layer being stable and having a prescribed melting-point temperature to melt the material layer to obtain a planar surface; and f) second-level electrical interconnections superimposed over said second insulator material layer.
Claim 18
Dependent Claim
144 words
A semiconductor device comprising: a) a substrate; b) first-level electrical interconnections disposed on said substrate; c) a barrier layer superimposed over said interconnections; d) a first layer of insulator material containing phosphorous and boron superimposed over said barrier layer, the concentration of boron being lower than 3% and the concentration of phosphorous being in the range of 6-9%, the first insulator material layer being stable and performing a gettering action on high-mobility ions; e) a second layer of insulator material containing phosphorous and boron directly over the first layer of insulator material, the concentration of boron being equal to 4-5% and the concentration of phosphorous being equal to 5%, the second insulator material layer being stable and having a prescribed melting-point temperature to melt the material layer to obtain a planar surface; and f) second-level electrical interconnections superimposed over said second insulator material layer.
Claim 19
Dependent Claim
26 words
The semiconductor device of claim 15, characterized in that the first layer has a boron concentration of approximately 2% and a phosphorous concentration of approximately 9%.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-28 | 2000-07-29 | 2001-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-28 | 2004-07-29 | 2005-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-28 | 2008-07-29 | 2009-01-28 | $7700.00 | Window Closed / Lapsed |