US5612914A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asymmetrical non-volatile memory cell, arrays and methods for fabricating same
Assignee: Texas Instruments Inc
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Filing: 1993-01-06
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Granted: 1997-03-18
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Expires: 2013-01-06
Abstract
Abstract A non-volatile memory cell (10) is formed in the face of a layer of semiconductor (12) of a first conductivity type, and includes a first heavily doped diffused region (14) and a second heavily doped diffused region (16) formed in semiconductor layer (12) to be of a second conductivity type opposite the first conductivity type. First heavily doped diffused region (14) and second heavily doped diffused region (16) are spaced by a channel area (18). A first lightly doped diffused region (20) is formed adjacent first heavily doped diffused region (14) to be of the second conductivity type. A second lightly doped diffused region (22) is formed in semiconductor layer (12) adjacent second heavily doped diffused region (16) to be of the second conductivity type. A floating gate (24) insulatively overlies the channel area and insulatively overlies a selected one of lightly doped diffused regions (20,22). A control gate (30) insulatively overlies floating gate (24).
Inventors
- 👤 David K. Liu
- 👤 Man Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:12
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
212 words
A method for operating a non-volatile memory cell comprising the steps of: providing the non-volatile memory cell, wherein said memory cell comprises: heavily doped source and drain regions formed in a layer of semiconductor, said source and drain regions spaced by a channel region; a lightly doped source region formed adjacent said heavily doped source region; a lightly doped drain region formed adjacent said heavily doped drain region; a floating gate conductor insulatively overlying said channel region and insulatively overlying said lightly doped drain region but not substantially overlying said lightly doped source region; and a control gate conductor capacitively coupled with said floating gate conductor; and programming said non-volatile memory cell by applying a first selected voltage to said control gate, a second selected voltage to said heavily doped source region and a third selected voltage to said heavily doped drain region wherein the application of said selected voltages creates a high electric field adjacent said lightly doped source region thereby injecting electrons from said lightly doped source region onto said floating gate; wherein said non-volatile memory cell is further read by applying about five volts to said control gate, applying about zero volts to said heavily doped source region and applying about 1.5 volts to said heavily doped drain region.
Claim 2
Independent Claim
212 words
A method for operating a non-volatile memory cell comprising the steps of: providing the non-volatile memory cell, wherein said memory cell comprises: heavily doped source and drain regions formed in a layer of semiconductor, said source and drain regions spaced by a channel region; a lightly doped source region formed adjacent said heavily doped source region; a lightly doped drain region formed adjacent said heavily doped drain region; a floating gate conductor insulatively overlying said channel region and insulatively overlying said lightly doped drain region but not substantially overlying said lightly doped source region; and a control gate conductor capacitively coupled with said floating gate conductor; and programming said non-volatile memory cell by applying a first selected voltage to said control gate, a second selected voltage to said heavily doped source region and a third selected voltage to said heavily doped drain region wherein the application of said selected voltages creates a high electric field adjacent said lightly doped source region thereby injecting electrons from said lightly doped source region onto said floating gate; wherein said non-volatile memory cell is further read by applying about five volts to said control gate, applying about zero volts to said heavily doped source region and applying about 1.5 volts to said heavily doped drain region.
Claim 3
Dependent Claim
31 words
The method of claim 1 wherein: said first selected voltage comprises about 12 volts; said second selected voltage comprises about 0 volts; and said third selected voltage comprises about 5 volts.
Claim 4
Dependent Claim
32 words
The method of claim 1 wherein said non-volatile memory cell is further erased by applying said selected voltages such that electrons travel from said floating gate to said heavily doped drain region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-03-17 | 2000-09-16 | 2001-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-17 | 2004-09-16 | 2005-03-18 | $3760.00 | Window Closed / Lapsed |
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