US5413962A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-level conductor process in VLSI fabrication utilizing an air bridge
Assignee: United Microelectronics Corp
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Filing: 1994-07-15
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Granted: 1995-05-09
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Expires: 2014-07-15
Abstract
Abstract This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.
Inventors
- 👤 Water Lur
- 👤 Jiunn Y. Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:34
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10W20/01; H10W20/071; H10W20/072; H10W20/43; H10W20/432; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424; H10W20/4432; H10W20/4435; H10W20/45; H10W20/46; H10W20/495; H10W20/074; H10W20/076; H10W20/077; Y; Y10; Y10S; Y10S148/00; Y10S148/073
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
254 words
A method of forming a multi-level conductor structure for VLSI circuits, comprising the steps of: providing a silicon substrate with circuits formed therein, a base dielectric layer formed on said substrate, and contact studs formed in said base dielectric layer making electrical contact with said circuits; forming a first electrode metal layer on said base dielectric layer and contact studs; etching a first electrode pattern in said first electrode metal layer; forming a first thin envelope oxide layer on said first electrode pattern and said base dielectric layer; forming a first inter-metal dielectric layer over said thin envelope oxide layer; forming a second thin envelope oxide layer over said first inter-metal dielectric layer; etching first inter-level vias with sidewalls in said first inter-metal dielectric layer, said first thin envelope oxide layer, and said second thin envelope oxide layer; forming a thin envelope oxide spacer on said sidewalls of said first inter-level vias; filling said first inter-level vias with first inter-level metal studs; forming a second electrode metal layer on said second thin envelope oxide layer and said first inter-level metal studs; forming a third thin envelope oxide layer on said second electrode metal layer; etching a second electrode pattern in said second electrode metal layer, said second envelope oxide layer, and said third envelope oxide layer said second electrode pattern having sidewalls; forming a thin envelope oxide spacer on said sidewalls of said second electrode pattern; removing all said inter-metal dielectric; and forming a passivation layer with poor step coverage over said silicon substrate.
Claim 2
Independent Claim
254 words
A method of forming a multi-level conductor structure for VLSI circuits, comprising the steps of: providing a silicon substrate with circuits formed therein, a base dielectric layer formed on said substrate, and contact studs formed in said base dielectric layer making electrical contact with said circuits; forming a first electrode metal layer on said base dielectric layer and contact studs; etching a first electrode pattern in said first electrode metal layer; forming a first thin envelope oxide layer on said first electrode pattern and said base dielectric layer; forming a first inter-metal dielectric layer over said thin envelope oxide layer; forming a second thin envelope oxide layer over said first inter-metal dielectric layer; etching first inter-level vias with sidewalls in said first inter-metal dielectric layer, said first thin envelope oxide layer, and said second thin envelope oxide layer; forming a thin envelope oxide spacer on said sidewalls of said first inter-level vias; filling said first inter-level vias with first inter-level metal studs; forming a second electrode metal layer on said second thin envelope oxide layer and said first inter-level metal studs; forming a third thin envelope oxide layer on said second electrode metal layer; etching a second electrode pattern in said second electrode metal layer, said second envelope oxide layer, and said third envelope oxide layer said second electrode pattern having sidewalls; forming a thin envelope oxide spacer on said sidewalls of said second electrode pattern; removing all said inter-metal dielectric; and forming a passivation layer with poor step coverage over said silicon substrate.
Claim 3
Dependent Claim
195 words
The method of claim 1, further comprising; after forming said thin envelope oxide spacer on said sidewalls of said second electrode pattern, before removing all said inter-metal dielectric, and before forming said passivation layer with poor step coverage; the steps of: forming a second layer of inter-metal dielectric over said second electrode pattern in said second electrode metal layer; forming a fourth thin envelope oxide layer over said second inter-metal dielectric layer; etching second inter-level vias with sidewalls in said second layer of inter-metal dielectric, said third thin envelope oxide layer, and said fourth thin envelope oxide layer; forming a thin envelope oxide spacer on said sidewalls of said second inter-level vias; filling said second inter-level vias with second inter-level metal studs; forming a third electrode metal layer on said fourth thin envelope oxide layer and said second inter-level metal studs; forming a fifth thin envelope oxide layer on said third electrode metal layer; etching a third electrode pattern in said third electrode metal layer, said fourth envelope oxide layer, and said fifth envelope oxide layer said pattern having sidewalls; and forming a thin envelope oxide spacer on said sidewalls of said third electrode pattern.
Claim 4
Dependent Claim
195 words
The method of claim 2, further comprising; after forming said thin envelope oxide spacer on said sidewalls of said third electrode pattern, before removing all said inter-metal dielectric, and before forming said passivation layer with poor step coverage; the steps of: forming a third layer of inter-metal dielectric over said third electrode pattern in said third electrode metal layer; forming a sixth thin envelope oxide layer over said third inter-metal dielectric layer; etching third inter-level vias with sidewalls in said third layer of inter-metal dielectric, said fifth thin envelope oxide layer, and said sixth thin envelope oxide layer; forming a thin envelope oxide spacer on said sidewalls of said third inter-level vias; filling said third inter-level vias with third inter-level metal studs; forming a fourth electrode metal layer on said sixth thin envelope oxide layer and said third inter-level metal studs; forming a seventh thin envelope oxide layer on said fourth electrode metal layer; etching a fourth electrode pattern in said fourth electrode metal layer, said sixth envelope oxide layer, and said seventh envelope oxide layer said pattern having sidewalls; and forming a thin envelope oxide spacer on said sidewalls of said fourth electrode pattern.
Claim 5
Dependent Claim
45 words
The method of claim 1 wherein said thin envelope oxide layers are SiO 2 with a thickness of between about 1000 and 2000 Angstroms and are formed using chemical vapor deposition with tetraethoxysilane (TEOS) or SiH 4 and O 2 or O 3 as precursors.
Claim 6
Dependent Claim
68 words
The method of claim 1 wherein said thin envelope oxide spacers are formed by depositing a layer of SiO 2 with a thickness of between about 1000 and 2000 Angstroms using chemical vapor deposition with tetraethoxysilane (TEOS) or SiH 4 and O 2 or O 3 as precursors and vertically anisotropically etching said layer of SiO 2 using CHF 3 , O 2 , Ar or the like.
Claim 7
Dependent Claim
19 words
The method of claim 1 wherein said inter-metal dielectric is Si 3 N 4 deposited using chemical vapor deposition.
Claim 8
Dependent Claim
25 words
The method of claim 6 wherein said inter-metal dielectric is removed by etching in a solution with a high etch selectivity for nitride to oxide.
Claim 9
Dependent Claim
20 words
The method of claim 7 wherein said solution with a high etch selectivity for nitride to oxide is phosphoric acid.
Claim 10
Dependent Claim
19 words
The method of claim 1 wherein said electrode metal is aluminum, an alloy of aluminum, tungsten, copper, or silver.
Claim 11
Dependent Claim
20 words
The method of claim 1 wherein said inter-level metal studs are aluminum, an alloy of aluminum, tungsten, copper, or silver.
Claim 12
Dependent Claim
13 words
The method of claim 1 wherein said base dielectric layer is borophosphosilicate glass.
Claim 13
Dependent Claim
24 words
The method of claim 1 wherein said passivation layer with poor step coverage is SiO 2 , Si 3 N 4 , or polyimide.
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