US5000818A
Expired / Lapsed
US
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Method of fabricating a high performance interconnect system for an integrated circuit
Assignee: National Semiconductor Corp
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Filing: 1990-05-18
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Granted: 1991-03-19
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Expires: 2010-05-18
Abstract
Abstract A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.
Inventors
- 👤 Michael E. Thomas
- 👤 Jeffrey D. Chinn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:47
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/057; H10W20/032; H10W20/033; H10W20/038; H10W20/039; H10W20/071; H10W20/072; H10W20/074; H10W20/075; H10W20/077; H10W20/40; H10W20/41; H10W20/42; H10W20/425; H10W20/43; H10W20/432; H10W20/45; H10W20/46; H10W44/00; H10W44/601
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
175 words
A method of fabricating a high performance interconnect structure for electrically connecting regions in a semiconductor substrate, said method comprising the steps of: (a) forming a first dielectric layer on said substrate; (b) forming contact holes in said first dielectric layer in predetermined spaced relation with said regions to expose contact areas thereon; (c) forming a first metal layer over said first dielectric layer and into said contact holes, making contact with said contact areas; (d) forming a first level of interconnects in said first metal layer; (e) forming a second dielectric layer, having a substantially planar upper surface, over said first level of interconnects; (f) forming at least one via opening in said second dielectric layer in predetermined spaced relation with said underlying first level of interconnects; (g) forming a second metal layer over said second dielectric layer and into said via openings, making contact with said exposed regions of said first level of interconnects; (h) patterning said second metal layer into a second level of interconnects; and (i) removing said second dielectric layer.
Claim 2
Independent Claim
175 words
A method of fabricating a high performance interconnect structure for electrically connecting regions in a semiconductor substrate, said method comprising the steps of: (a) forming a first dielectric layer on said substrate; (b) forming contact holes in said first dielectric layer in predetermined spaced relation with said regions to expose contact areas thereon; (c) forming a first metal layer over said first dielectric layer and into said contact holes, making contact with said contact areas; (d) forming a first level of interconnects in said first metal layer; (e) forming a second dielectric layer, having a substantially planar upper surface, over said first level of interconnects; (f) forming at least one via opening in said second dielectric layer in predetermined spaced relation with said underlying first level of interconnects; (g) forming a second metal layer over said second dielectric layer and into said via openings, making contact with said exposed regions of said first level of interconnects; (h) patterning said second metal layer into a second level of interconnects; and (i) removing said second dielectric layer.
Claim 3
Dependent Claim
44 words
The method in accordance with claim 1 additionally comprising the steps of: (j) repeating steps (e) through (h) at least once to form at least a third level of interconnects; and (k) removing each dielectric layer formed as a result of performing step (e).
Claim 4
Dependent Claim
34 words
The method in accordance with claim 2 wherein step (a) comprises the steps of: (i) forming a dielectric layer on said substrate; and (ii) forming an etch stop dielectric layer over said dielectric layer.
Claim 5
Dependent Claim
61 words
The method in accordance with claim 3 wherein step (c) comprises the steps of: (i) forming an electrically conductive adhesion layer over said etch stop dielectric layer and into said contact holes, making contact with said contact areas; (ii) forming an electrically conductive barrier layer over said adhesion layer; and (iii) forming a metal layer over said electrically conductive barrier layer.
Claim 6
Dependent Claim
47 words
The method in accordance with claim 4 wherein step (e) comprises the steps of: (i) forming a protective dielectric layer over said first level of interconnects; (ii) forming a dielectric layer over said first protective dielectric layer; and (iii) planarizing the upper surface of said dielectric layer.
Claim 7
Dependent Claim
55 words
The method in accordance with claim 5 wherein step (g) comprises the steps of: (i) forming an electrically conductive adhesion layer over said second dielectric layer and into said via openings, making contact with said exposed regions of said first level of interconnects; and (ii) forming a metal layer over said electrically conductive adhesion layer.
Claim 8
Dependent Claim
33 words
The method in accordance with claim 1 additionally comprising the step of forming a dielectric layer around said interconnects, leaving a gap between those portions of the dielectric layer which surround adjacent interconnects.
Claim 9
Dependent Claim
21 words
The method in accordance with claim 7 wherein said additional step comprises depositing a layer of silicon dioxide around said interconnects.
Claim 10
Dependent Claim
21 words
The method in accordance with claim 7 additionally comprising the step of forming an electrically conductive layer around said dielectric layer.
Claim 11
Dependent Claim
30 words
The method in accordance with claim 7 additionally comprising the step of forming an electrically conductive layer around said dielectric layer, said electrically conductive layer substantially filling in said gaps.
Claim 12
Dependent Claim
23 words
The method in accordance with claim 10 wherein said additional step comprises depositing a layer of tungsten around said layer of silicon dioxide.
Claim 13
Independent Claim
235 words
A method of fabricating a high performance interconnect structure for electrically connecting regions in a semiconductor substrate, said method comprising the steps of: (a) forming a first dielectric layer on said substrate; (b) forming contact holes in said first dielectric layer in predetermined spaced relation with said regions to expose contact areas thereon; (c) forming a first layer of a first electrically conductive material over said dielectric layer and into said contact holes, making contact with said contact areas; (d) forming a second layer of a second electrically conductive material over said first electrically conductive layer; (e) forming at least one post in said second electrically conductive layer; (f) forming a first level of interconnects in said first electrically conductive layer, said at least one post being in predetermined spaced relation to and in contact with said first level of interconnects; (g) forming a second dielectric layer, having a substantially planar upper surface, over said at least one post and said first level of interconnects; (h) etching back said second dielectric layer until the top surface of said at least one post is exposed; (i) forming a third electrically conductive layer, comprising said first electrically conductive material, over said second dielectric and into contact with said exposed top surface of said at least one post; (j) patterning said third electrically conductive layer into a second level of interconnects; and (k) removing said second dielectric layer.
Claim 14
Independent Claim
235 words
A method of fabricating a high performance interconnect structure for electrically connecting regions in a semiconductor substrate, said method comprising the steps of: (a) forming a first dielectric layer on said substrate; (b) forming contact holes in said first dielectric layer in predetermined spaced relation with said regions to expose contact areas thereon; (c) forming a first layer of a first electrically conductive material over said dielectric layer and into said contact holes, making contact with said contact areas; (d) forming a second layer of a second electrically conductive material over said first electrically conductive layer; (e) forming at least one post in said second electrically conductive layer; (f) forming a first level of interconnects in said first electrically conductive layer, said at least one post being in predetermined spaced relation to and in contact with said first level of interconnects; (g) forming a second dielectric layer, having a substantially planar upper surface, over said at least one post and said first level of interconnects; (h) etching back said second dielectric layer until the top surface of said at least one post is exposed; (i) forming a third electrically conductive layer, comprising said first electrically conductive material, over said second dielectric and into contact with said exposed top surface of said at least one post; (j) patterning said third electrically conductive layer into a second level of interconnects; and (k) removing said second dielectric layer.
Claim 15
Dependent Claim
44 words
The method in accordance with claim 12 additionally comprising the steps of: (l) repeating steps (g) through (j) at least once to form at least a third level of interconnects; and (m) removing each dielectric layer formed as a result of performing step (g).
Claim 16
Dependent Claim
56 words
The method in accordance with claim 13 wherein step (e) comprises the steps of: (i) forming a mask defining at least one post region; (ii) etching said second electrically conductive layer around said mask with a second etchant which reacts with said second electrically conductive material but is substantially unreactive with said first electrically conductive material.
Claim 17
Dependent Claim
65 words
The method in accordance with claim 14 wherein step (f) comprises the steps of: (i) forming a mask defining a pattern for said first level of interconnects; and (ii) etching said first electrically conductive material around said mask using an etchant which reacts with said first electrically conductive material but is substantially unreactive with said second electrically conductive material and said underlying first dielectric layer.
Claim 18
Dependent Claim
63 words
The method in accordance with claim 15 wherein comprises the steps of: (i) forming a mask defining a pattern for said second level of interconnects; and (ii) etching said first electrically conductive material around said mask using an etchant which reacts with said first electrically conductive material but is substantially unreactive with said second electrically conductive material and said underlying second dielectric layer.
Claim 19
Dependent Claim
50 words
The method in accordance with claim 12 wherein steps (c) and (i) comprise the steps of: (i) forming a first layer of an aluminum-silicon mixture; (ii) forming a first titanium layer over said first aluminum-silicon layer; and (iii) forming at least a second aluminum-silicon layer over said first titanium layer.
Claim 20
Dependent Claim
46 words
The method in accordance with claim 17 additionally comprising the steps of: (iv) forming at least a second titanium layer over said second aluminum-silicon layer; (v) forming a third aluminum-silicon layer over said second titanium layer; (vi) forming a protective layer over the third aluminum-silicon layer.
Claim 21
Dependent Claim
13 words
The method in accordance with claim 18 wherein said protective layer comprises tungsten.
Claim 22
Independent Claim
253 words
A method of fabricating a high performance interconnect structure for electrically connecting regions in a semiconductor substrate, said method comprising the steps of: (a) forming a first dielectric layer on said substrate, said first dielectric layer having a substantially planar upper surface; (b) forming contact holes in said first dielectric layer in predetermined spaced relation with said regions to expose contact areas thereon; (c) forming electrically conductive posts in said contact holes making contact with said contact areas, each post having an upper surface which is substantially coplanar with the upper surface of said first dielectric layer; (d) forming a first electrically conductive layer over said dielectric layer and into contact with the upper surfaces of said posts; (e) forming a first level of interconnects in said first electrically conductive layer; (f) forming a second dielectric layer, having a substantially planar upper surface, over said first level of interconnects; (g) forming at least one via opening in said second dielectric layer in predetermined spaced relation with said underlying first level of interconnects; (h) forming an electrically conductive post in each via opening, said electrically conductive post having an upper surface which is substantially coplanar with the upper surface of said second dielectric layer; (i) forming a second electrically conductive layer over said second dielectric layer and into contact with the upper surface of the post in each via in said second dielectric layer; (j) patterning said second electrically conductive layer into a second level of interconnects; and (k) removing said second dielectric layer.
Claim 23
Independent Claim
253 words
A method of fabricating a high performance interconnect structure for electrically connecting regions in a semiconductor substrate, said method comprising the steps of: (a) forming a first dielectric layer on said substrate, said first dielectric layer having a substantially planar upper surface; (b) forming contact holes in said first dielectric layer in predetermined spaced relation with said regions to expose contact areas thereon; (c) forming electrically conductive posts in said contact holes making contact with said contact areas, each post having an upper surface which is substantially coplanar with the upper surface of said first dielectric layer; (d) forming a first electrically conductive layer over said dielectric layer and into contact with the upper surfaces of said posts; (e) forming a first level of interconnects in said first electrically conductive layer; (f) forming a second dielectric layer, having a substantially planar upper surface, over said first level of interconnects; (g) forming at least one via opening in said second dielectric layer in predetermined spaced relation with said underlying first level of interconnects; (h) forming an electrically conductive post in each via opening, said electrically conductive post having an upper surface which is substantially coplanar with the upper surface of said second dielectric layer; (i) forming a second electrically conductive layer over said second dielectric layer and into contact with the upper surface of the post in each via in said second dielectric layer; (j) patterning said second electrically conductive layer into a second level of interconnects; and (k) removing said second dielectric layer.
Claim 24
Dependent Claim
44 words
The method in accordance with claim 20 additionally comprising the steps of: (l) repeating steps (f) through (j) at least once to form at least a third level of interconnects; and (m) removing each dielectric layer formed as a result of performing step (f).
Claim 25
Dependent Claim
56 words
The method in accordance with claim 20 wherein step (d) and step (i) each comprises the steps of (i) forming a first layer of an aluminum-silicon mixture; (ii) forming a first layer of titanium over said first aluminum-silicon layer; and (iii) forming at least a second layer of an aluminum-silicon mixture over said first titanium layer.
Claim 26
Dependent Claim
49 words
The method in accordance with claim 22 additionally comprising the steps of: (iv) forming at least a second layer of titanium over said second aluminum-silicon layer; (v) forming a third aluminum-silicon layer over said second titanium layer; and (vi) forming a protective layer over the third layer of aluminum-silicon.
Claim 27
Dependent Claim
20 words
The method in accordance with claim 22 where said aluminum-silicon mixture comprises approximately 1% to 1.5% of silicon by weight.
Claim 28
Dependent Claim
13 words
The method in accordance with claim 24 wherein the protective layer comprises tungsten.
Claim 29
Dependent Claim
43 words
The method in accordance with claim 25 wherein said aluminum-silicon layers are formed to a thickness of approximately 2500A; said titanium layers are formed to a thickness of approximately of 200A; and said tungten protective layer is formed to a thickness of 1000A.
Claim 30
Dependent Claim
51 words
The method in accordance with claim 1 were in steps (c) and (g), each comprises the steps of: (i) forming a first layer of aluminum-silicon mixture; (ii) forming a first layer of titanium over said first aluminum-silicon layer (iii) forming at least a second aluminum-silicon layer over said first titanium layer.
Claim 31
Dependent Claim
44 words
The method in accordance with claim 27 additionally comprises the steps of: (iv) forming a second titanium layer over said second aluminum-silicon layer; (v) forming a third aluminum-silicon layer over said second titanium layer; (vi) forming a protective layer over said third aluminum-silicon layer.
Claim 32
Dependent Claim
13 words
The method in accordance with claim 28 wherein said protective layer comprises tungsten.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-18 | 1994-09-17 | 1995-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-18 | 1998-09-17 | 1999-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-18 | 2002-09-17 | 2003-03-19 | $7700.00 | Window Closed / Lapsed |