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US3846166A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of producing multilayer wiring structure of integrated circuit

Assignee: Hitachi Ltd
•
Filing: 1972-09-25
•
Granted: 1974-11-05
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Expires: 1992-09-25
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Abstract

Abstract 1. A METHOD OF PRODUCING A MULTILAYER WIRING STRUCTURE FOR AN INTERGRATED CIRCUIT, COMPRISING THE STEPS OF: (A) FORMING A FIRST WIRING CONDUCTOR LAYER OF A PREDETERMINED PATTERN ON THE SURFACE OF A SUBSTRATE; (B) FORMING A RESIN LAYER ON THE RESULTING ENTIRE EXPOSED AREA OF SAID SUBSTRATE AND ON SAID WIRING CONDUCTOR LAYER FORMED ON SAID SUBSTRATE; (C) FORMING, ON SAID RESIN LAYR, A METALLIC FILM WHICH IS SELECTIVELY ETETCHED TO FORM OPENINGS OF A PREDETERMINED SHAPE AT PREDETERMINED POSITIONS FOR CONNECTION BETWEEN THE WIRING CONDUCTOR LAYERS; (D) PROVIDING OPENINGS AT PREDETERMINED POSITIONS IN SAID RESIN LAYER USING SAID METALLIC FILM AS A MASK BY PHYSICALLY ETCHING SAID RESIN LAYER WITH A PLASMA DISCHARGE ATMOSPHERE, SAID OPENINGS REACHING SAID WIRING CODUCTOR LAYER LOCATED BENEATH SAID RESIN LAYER; (E) REMOVING SAID METALLIC FILM FORMED BY THE STEPS (C) WITH AN ETCHANT; AND (F) FORMING A SECOND WIRING CONDUCTOR LAYER OF A PREDETERMINED PATTERN, WHICH IS ELECTRICALLY AND MECHANICALLY CONNECTED WITH THE EXPOSED PARTS OF SAID FIRST WIRING CONDUCTOR LAYER PARTIALLY EXPOSED THROUGH THE STEP (D) AND WHICH EXTENDS ON SAID RESIN LAYER FORMED BY THE STEP (B).

Inventors

  • 👤 A Saiki
  • 👤 K Sato
  • 👤 T Mori
  • 👤 S Harada

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 23:20
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/0011; H05K3/0017; H05K3/0041; H10; H10P; H10P50/00; H10P50/60; H10P50/66; H10P50/663; H10P50/667; H10W; H10W20/00; H10W20/40; H10W70/00; H10W70/01; H10W70/05; H10W70/60; H10W70/611; H10W74/00; H10W74/40; H10W74/47; H05K2203/00; H05K2203/05; H05K2203/0548; H05K2203/0554; H05K3/46; H05K3/4644; H05K3/4652

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 186 words
A METHOD OF PRODUCING A MULTILAYER WIRING STRUCTURE FOR AN INTERGRATED CIRCUIT, COMPRISING THE STEPS OF: (A) FORMING A FIRST WIRING CONDUCTOR LAYER OF A PREDETERMINED PATTERN ON THE SURFACE OF A SUBSTRATE; (B) FORMING A RESIN LAYER ON THE RESULTING ENTIRE EXPOSED AREA OF SAID SUBSTRATE AND ON SAID WIRING CONDUCTOR LAYER FORMED ON SAID SUBSTRATE; (C) FORMING, ON SAID RESIN LAYR, A METALLIC FILM WHICH IS SELECTIVELY ETETCHED TO FORM OPENINGS OF A PREDETERMINED SHAPE AT PREDETERMINED POSITIONS FOR CONNECTION BETWEEN THE WIRING CONDUCTOR LAYERS; (D) PROVIDING OPENINGS AT PREDETERMINED POSITIONS IN SAID RESIN LAYER USING SAID METALLIC FILM AS A MASK BY PHYSICALLY ETCHING SAID RESIN LAYER WITH A PLASMA DISCHARGE ATMOSPHERE, SAID OPENINGS REACHING SAID WIRING CODUCTOR LAYER LOCATED BENEATH SAID RESIN LAYER; (E) REMOVING SAID METALLIC FILM FORMED BY THE STEPS (C) WITH AN ETCHANT; AND (F) FORMING A SECOND WIRING CONDUCTOR LAYER OF A PREDETERMINED PATTERN, WHICH IS ELECTRICALLY AND MECHANICALLY CONNECTED WITH THE EXPOSED PARTS OF SAID FIRST WIRING CONDUCTOR LAYER PARTIALLY EXPOSED THROUGH THE STEP (D) AND WHICH EXTENDS ON SAID RESIN LAYER FORMED BY THE STEP (B).
Claim 2
Independent Claim 186 words
A METHOD OF PRODUCING A MULTILAYER WIRING STRUCTURE FOR AN INTERGRATED CIRCUIT, COMPRISING THE STEPS OF: (A) FORMING A FIRST WIRING CONDUCTOR LAYER OF A PREDETERMINED PATTERN ON THE SURFACE OF A SUBSTRATE; (B) FORMING A RESIN LAYER ON THE RESULTING ENTIRE EXPOSED AREA OF SAID SUBSTRATE AND ON SAID WIRING CONDUCTOR LAYER FORMED ON SAID SUBSTRATE; (C) FORMING, ON SAID RESIN LAYR, A METALLIC FILM WHICH IS SELECTIVELY ETETCHED TO FORM OPENINGS OF A PREDETERMINED SHAPE AT PREDETERMINED POSITIONS FOR CONNECTION BETWEEN THE WIRING CONDUCTOR LAYERS; (D) PROVIDING OPENINGS AT PREDETERMINED POSITIONS IN SAID RESIN LAYER USING SAID METALLIC FILM AS A MASK BY PHYSICALLY ETCHING SAID RESIN LAYER WITH A PLASMA DISCHARGE ATMOSPHERE, SAID OPENINGS REACHING SAID WIRING CODUCTOR LAYER LOCATED BENEATH SAID RESIN LAYER; (E) REMOVING SAID METALLIC FILM FORMED BY THE STEPS (C) WITH AN ETCHANT; AND (F) FORMING A SECOND WIRING CONDUCTOR LAYER OF A PREDETERMINED PATTERN, WHICH IS ELECTRICALLY AND MECHANICALLY CONNECTED WITH THE EXPOSED PARTS OF SAID FIRST WIRING CONDUCTOR LAYER PARTIALLY EXPOSED THROUGH THE STEP (D) AND WHICH EXTENDS ON SAID RESIN LAYER FORMED BY THE STEP (B).

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-11-04 1978-05-06 1978-11-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-11-04 1982-05-06 1982-11-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-11-04 1986-05-06 1986-11-05 $7700.00 Window Closed / Lapsed

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