Patent US6140181A successfully refreshed from Google Patents.
US6140181A
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US
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Memory using insulator traps
Assignee: Micron Technology Inc
•
Filing: 1999-09-10
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Granted: 2000-10-31
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Expires: 2019-09-10
Abstract
Abstract A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.
Inventors
- 👤 Leonard Forbes
- 👤 Joseph E. Geusic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:00
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5671; B; B82; B82Y; B82Y10/00; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/0458; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/687; H10D30/688; G11C2216/00; G11C2216/02; G11C2216/08; H10D30/69; H10D30/691
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
50 words
A method of forming a memory cell on a substrate, the method comprising: forming transistor source and drain regions in the substrate; forming a gate insulator having a thickness; forming electrically isolated point defect trap sites in the gate insulator; and forming a control gate electrode on the gate insulator.
Claim 2
Independent Claim
50 words
A method of forming a memory cell on a substrate, the method comprising: forming transistor source and drain regions in the substrate; forming a gate insulator having a thickness; forming electrically isolated point defect trap sites in the gate insulator; and forming a control gate electrode on the gate insulator.
Claim 3
Dependent Claim
31 words
The method of claim 1, wherein forming the trap sites comprises ion implanting impurities at an areal concentration that is approximately between 10 12 and 10 15 impurities per square centimeter.
Claim 4
Dependent Claim
20 words
The method of claim 2, wherein the impurities are selected from the group consisting essentially of aluminum, silicon, and arsenic.
Claim 5
Dependent Claim
29 words
The method of claim 2, wherein the impurities are implanted in the insulator at a distance from the substrate that is approximately 1/3 of the thickness of the insulator.
Claim 6
Dependent Claim
19 words
The method of claim 1, wherein forming the trap sites is carried out simultaneously with forming the gate insulator.
Claim 7
Dependent Claim
20 words
The method of claim 1, wherein forming the trap sites includes oxidizing silicon to form a silicon dioxide gate insulator.
Claim 8
Dependent Claim
24 words
The method of claim 1, wherein forming the trap sites further comprises annealing the gate insulator to adjust a density of the trap sites.
Claim 9
Independent Claim
49 words
A method of forming a memory cell on a substrate, the method comprising: forming transistor source and drain regions in the substrate; forming a gate insulator having a thickness and also having electrically isolated point defect trap sites; and forming a control gate electrode on the gate it insulator.
Claim 10
Independent Claim
49 words
A method of forming a memory cell on a substrate, the method comprising: forming transistor source and drain regions in the substrate; forming a gate insulator having a thickness and also having electrically isolated point defect trap sites; and forming a control gate electrode on the gate it insulator.
Claim 11
Dependent Claim
34 words
The method of claim 8, wherein forming the gate insulator with trap sites comprises ion implanting impurities at an areal concentration that is approximately between 10 12 and 10 15 impurities per square centimeter.
Claim 12
Dependent Claim
20 words
The method of claim 9, wherein the impurities are selected from the group consisting essentially of aluminum, silicon, and arsenic.
Claim 13
Dependent Claim
29 words
The method of claim 9, wherein the impurities are implanted in the insulator at a distance from the substrate that is approximately 1/3 of the thickness of the insulator.
Claim 14
Dependent Claim
27 words
The method of claim 8, wherein the trap sites have a Gaussian distribution and are located relatively close to the interface between the gate and the substrate.
Claim 15
Dependent Claim
20 words
The method of claim 8, wherein forming the trap sites includes oxidizing silicon to form a silicon dioxide gate insulator.
Claim 16
Dependent Claim
38 words
The method of claim 8, wherein forming the trap sites further comprises annealing the gate insulator to adjust a density of the trap sites to avoid agglomeration of point defect trap sites into nanocrystals of the implanted impurities.
Claim 17
Independent Claim
74 words
A method of forming a memory cell on a substrate, the method comprising: forming transistor source and drain regions in the substrate; forming a gate insulator of amorphous silicon dioxide by thermal oxidation of the silicon substrate; adjusting the oxidizing ambient during the thermal oxidation while performing an ion implantation to create point defect trap sites in the gate insulator having a desired density; and forming a control gate electrode on the gate insulator.
Claim 18
Independent Claim
74 words
A method of forming a memory cell on a substrate, the method comprising: forming transistor source and drain regions in the substrate; forming a gate insulator of amorphous silicon dioxide by thermal oxidation of the silicon substrate; adjusting the oxidizing ambient during the thermal oxidation while performing an ion implantation to create point defect trap sites in the gate insulator having a desired density; and forming a control gate electrode on the gate insulator.
Claim 19
Dependent Claim
29 words
The method of claim 15, wherein the ion implantation step implants impurities at an areal concentration that is approximately between 10 12 and 10 15 impurities per square centimeter.
Claim 20
Dependent Claim
20 words
The method of claim 16, wherein the impurities are selected from the group consisting essentially of aluminum, silicon, and arsenic.
Claim 21
Dependent Claim
29 words
The method of claim 16, wherein the impurities are implanted in the insulator at a distance from the substrate that is approximately 1/3 of the thickness of the insulator.
Claim 22
Dependent Claim
18 words
The method of claim 15, wherein the ion implantation is carried out simultaneously with forming the gate insulator.
Claim 23
Dependent Claim
19 words
The method of claim 15, wherein the ion implantation includes oxidizing silicon to form a silicon dioxide gate insulator.
Claim 24
Dependent Claim
23 words
The method of claim 15, wherein the ion implantation further comprises annealing the gate insulator to adjust a density of the trap sites.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-31 | 2004-05-01 | 2004-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-31 | 2008-05-01 | 2008-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-31 | 2012-05-01 | 2012-10-31 | $7700.00 | Window Closed / Lapsed |