Latch-up free power MOS-bipolar transistor

Claim 2

A MOS bipolar transistor comprising: a silicon carbide npn bipolar transistor on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and an epitaxial p-type base layer formed as a mesa on said n-type drift layer; a silicon carbide nMOSFET in said n-type drift layer including spaced apart n-type source and drain regions with a gate region therebetween and adjacent said npn bipolar transistor so as to provide base current to said npn bipolar transistor when said bipolar transistor is in a conductive state; means for converting electron current flowing between said source and said drain into hole current for injection into said p-type base layer; and means for reducing field crowding associated with an insulating layer of said nMOSFET.

Claim 3

A MOS bipolar transistor according to claim 1 wherein said means for converting comprises: a region of p-type conductivity silicon carbide in said p-type base layer and having a higher carrier concentration than said p-type base layer; and an electrically conductive strap for electrically connecting the n-type source region of said nMOSFET to said region of p-type conductivity silicon carbide.

Claim 4

A MOS bipolar transistor according to claim 1, wherein said means for reducing field crowing comprises a region of p-type conductivity silicon carbide formed in said drift layer beneath and spaced apart from said insulating layer and extending to said base layer.

Claim 5

A MOS bipolar transistor according to claim 1, wherein sidewalls of said mesa includes a step portion and wherein said means for converting comprises: a region of p-type conductivity silicon carbide in said p-type base layer at said step portion having a higher carrier concentration than said p-type base layer; and an electrically conductive strap for electrically connecting the n-type source region of said nMOSFET to said region of p-type conductivity silicon carbide.

Claim 6

A MOS bipolar transistor according to claim 1, wherein said mesa has sloped sidewalls wherein the slope of the sidewalls provides a predefined doping profile associated with said means for reducing field crowding.

Claim 7

A MOS bipolar transistor according to claim 1, wherein said nMOSFET is an accumulation mode nMOSFET.

Claim 8

A unit cell of a MOS bipolar transistor comprising: an n-type bulk single crystal silicon carbide substrate; an n-type silicon carbide drift layer adjacent said n-type conductivity bulk single crystal silicon carbide substrate, said n-type drift layer having a carrier concentration of less than said n-type silicon carbide substrate; a p-type epitaxial silicon carbide base layer formed on said n-type silicon carbide drift layer; a first n-type region of silicon carbide formed in said p-type base layer adjacent a surface opposite said n-type silicon carbide drift layer; wherein said p-type epitaxial silicon carbide base layer is formed as a mesa having a sidewall which extends through said p-type epitaxial silicon carbide base layer and to said n-type drift layer; an insulating layer formed on said n-type drift layer adjacent and disposed from said sidewall; a second n-type conductivity region of silicon carbide formed in said drift layer adjacent said sidewalls of said mesa, said second-n-type conductivity region having a higher carrier concentration than said drift layer; a gate contact on said insulating layer and extending over a portion of said first n-type region; a collector contact on a surface of said silicon carbide substrate opposite said drift layer; a first p-type region of silicon carbide in said base layer and a second p-type region form adjacent said second n-type conductivity region and extending into said n-type drift region below said second n-type conductivity region and below said gate contact, said first and second p-type regions being electrically connected and having a carrier concentration greater than the carrier concentration of said p-type epitaxial base layer and said first p-type region being formed so as to convert electrons flowing through said first n-type region into holes for injection into said p-type base layer; a conductive strap formed at base of said sidewall so as to electrically connect said second n-type conductivity region with said first p-type region of silicon carbide; and an emitter contact on said first n-type region of silicon carbide.

Claim 9

A unit cell of a MOS bipolar transistor comprising: an n-type bulk single crystal silicon carbide substrate; an n-type silicon carbide drift layer adjacent said n-type conductivity bulk single crystal silicon carbide substrate, said n-type drift layer having a carrier concentration of less than said n-type silicon carbide substrate; a p-type epitaxial silicon carbide base layer formed on said n-type silicon carbide drift layer; a first n-type region of silicon carbide formed in said p-type base layer adjacent a surface opposite said n-type silicon carbide drift layer; wherein said p-type epitaxial silicon carbide base layer is formed as a mesa having a sidewall which extends through said p-type epitaxial silicon carbide base layer and to said n-type drift layer; an insulating layer formed on said n-type drift layer adjacent and disposed from said sidewall; a second n-type conductivity region of silicon carbide formed in said drift layer adjacent said sidewalls of said mesa, said second-n-type conductivity region having a higher carrier concentration than said drift layer; a gate contact on said insulating layer and extending over a portion of said first n-type region; a collector contact on a surface of said silicon carbide substrate opposite said drift layer; a first p-type region of silicon carbide in said base layer and a second p-type region form adjacent said second n-type conductivity region and extending into said n-type drift region below said second n-type conductivity region and below said gate contact, said first and second p-type regions being electrically connected and having a carrier concentration greater than the carrier concentration of said p-type epitaxial base layer and said first p-type region being formed so as to convert electrons flowing through said first n-type region into holes for injection into said p-type base layer; a conductive strap formed at base of said sidewall so as to electrically connect said second n-type conductivity region with said first p-type region of silicon carbide; and an emitter contact on said first n-type region of silicon carbide.

Claim 10

The unit cell according to claim 7 wherein the first and second regions of p-type silicon carbide comprise a continuous region of p-type silicon carbide formed in said base layer adjacent a sidewall of said mesa and said second n-type conductivity region and extending into and below said gate contact.

Claim 11

The unit cell according to claim 7, wherein the sidewall has a slope of less than about 60 degrees.

Claim 12

The unit cell according to claim 9, wherein the slope of the sidewall is selected so as to produce said second p-type regions of silicon carbide when p-type ions are implanted at a predetermined depth in said drift layer.

Claim 13

The unit cell according to claim 7, wherein said sidewall comprises two sidewalls so as to provide a step in the sidewall of said mesa; wherein said first and second p-type regions of silicon carbide comprise: a first p-type region of silicon carbide formed in said p-type epitaxial base layer adjacent said step; and a second p-type region of silicon carbide formed in said n-type drift layer adjacent said second n-type conductivity region, extending into said n-type drift layer below said gate contact and extending to said p-type base layer.

Claim 14

The unit cell according to claim 11, wherein said second p-type region is formed so as to be exposed at a surface of if said drift layer and wherein said conductive strap electrically connects said first p-type region with said second p-type region and said second n-type region.

Claim 15

The unit cell according to claim 12, further comprising an insulating layer formed on the sidewall of said mesa between said drift layer and said step and extending onto said step and wherein said conducting strap is formed on said insulating layer.

Claim 16

The unit cell according to claim 7, wherein said p-type base layer has a thickness of from about 0.3 μm to about 5 μm.

Claim 17

The unit cell according to claim 7, wherein said n-type drift region has a thickness of from about 3 μm to about 500 μm.

Claim 18

The unit cell according to claim 7, wherein said n-type drift region has a carrier concentration of from about 10 12 to about 10 17 cm -3 .

Claim 19

The unit cell according to claim 7, wherein said p-type epitaxial base layer has a carrier concentration of from about 10 16 to about 10 18 cm -3 .

Claim 20

A unit cell according to claim 7 wherein said insulating layer comprises an oxide layer.

Claim 21

A MOS gated bipolar transistor comprising a plurality of the unit cells of claim 7.

Claim 22

A unit cell according to claim 7, wherein said second p-type region extends beneath the gate contact a distance of from about 3 μm to about 12 μm.

Claim 23

A unit cell according to claim 7, wherein the second n-type conductivity region extends into the n-type drift layer to a depth of from about 0.3 μm to about 5 μm.