Latch-up free power UMOS-bipolar transistor

Claim 1

A MOS bipolar transistor comprising: a silicon carbide npn bipolar transistor on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and a p-type base layer; a silicon carbide nMOSFET in said p-type base layer including spaced apart n-type source and drain regions with a gate region therebetween and adjacent said npn bipolar transistor so as to provide base current to said npn bipolar transistor when said bipolar transistor is in a conductive state; and means for converting electron current flowing between said source and said drain into hole current for injection into said p-type base layer.

Claim 20

A method of forming a UMOS bipolar transistor comprising: forming an n-type silicon carbide drift layer on an n-type conductivity bulk single crystal silicon carbide substrate, said n-type drift layer having a carrier concentration of less than said n-type silicon carbide substrate; forming a p-type silicon carbide base layer on said n-type silicon carbide drift layer; forming a first n-type region of silicon carbide in said p-type base layer; forming a first gate trench formed in said p-type base layer and extending through said base layer and said first n-type region to said drift layer so as to provide a portion of said n-type region as a portion of the sidewall of said gate trench; forming an insulating layer formed on the bottom and sidewalls of said gate trench; forming a second n-type conductivity region of silicon carbide formed in said base layer adjacent and disposed from said gate trench; forming a gate contact formed on said insulating layer and extending over a portion of said first n-type region; forming a collector contact formed on a surface of said silicon carbide substrate opposite said drift layer; forming a p-type region of silicon carbide formed in said base layer and disposed between said first n-type region and said second n-type region, said p-type region having a carrier concentration greater than the carrier concentration of said p-type base layer and formed so as to convert electrons flowing through said first n-type region into holes for injection into said p-type base layer; and forming an emitter contact formed on said second n-type region of silicon carbide.

Claim 21

A method of forming a UMOS bipolar transistor comprising: forming an n-type silicon carbide drift layer on an n-type conductivity bulk single crystal silicon carbide substrate, said n-type drift layer having a carrier concentration of less than said n-type silicon carbide substrate; forming a p-type silicon carbide base layer on said n-type silicon carbide drift layer; forming a first n-type region of silicon carbide in said p-type base layer; forming a first gate trench formed in said p-type base layer and extending through said base layer and said first n-type region to said drift layer so as to provide a portion of said n-type region as a portion of the sidewall of said gate trench; forming an insulating layer formed on the bottom and sidewalls of said gate trench; forming a second n-type conductivity region of silicon carbide formed in said base layer adjacent and disposed from said gate trench; forming a gate contact formed on said insulating layer and extending over a portion of said first n-type region; forming a collector contact formed on a surface of said silicon carbide substrate opposite said drift layer; forming a p-type region of silicon carbide formed in said base layer and disposed between said first n-type region and said second n-type region, said p-type region having a carrier concentration greater than the carrier concentration of said p-type base layer and formed so as to convert electrons flowing through said first n-type region into holes for injection into said p-type base layer; and forming an emitter contact formed on said second n-type region of silicon carbide.

Claim 27

A method of forming a MOS gated bipolar transistor comprising the steps of: forming an n-type silicon carbide drift layer on an n-type bulk single crystal silicon carbide substrate; forming a p-type silicon carbide base layer on the n-type silicon carbide drift layer; implanting through a first mask ions so as to form a n-type regions of silicon carbide in the base layer to provide an emitter region and a drain region; implanting through a second mask ions so as to form a p-type region of silicon carbide adjacent the source region; etching a trench through a portion of the n-type source region and through the base layer and into the drift layer so as provide a gate trench; forming an insulating layer on exposed surfaces of the base layer and the trench; forming and patterning an ohmic contact in the trench and on the base layer so as to provide a gate contact; removing a portion of the insulating layer to expose the emitter region formed in the base layer; forming an emitter contact on the exposed emitter region; and forming a source/emitter contact on a surface of the silicon carbide substrate opposite the drift layer.

Claim 28

A method of forming a MOS gated bipolar transistor comprising the steps of: forming an n-type silicon carbide drift layer on an n-type bulk single crystal silicon carbide substrate; forming a p-type silicon carbide base layer on the n-type silicon carbide drift layer; implanting through a first mask ions so as to form a n-type regions of silicon carbide in the base layer to provide an emitter region and a drain region; implanting through a second mask ions so as to form a p-type region of silicon carbide adjacent the source region; etching a trench through a portion of the n-type source region and through the base layer and into the drift layer so as provide a gate trench; forming an insulating layer on exposed surfaces of the base layer and the trench; forming and patterning an ohmic contact in the trench and on the base layer so as to provide a gate contact; removing a portion of the insulating layer to expose the emitter region formed in the base layer; forming an emitter contact on the exposed emitter region; and forming a source/emitter contact on a surface of the silicon carbide substrate opposite the drift layer.