Power metal-oxide-semiconductor field effect transistor

Claim 2

A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a body region of a second conductivity type; and a drain region of said first conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said body region into said drain region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said drain region and said insulating layer and adjacent to said corner, said shield region being of said first conductivity type and being doped to a lesser degree than said drain region, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 3

The metal-oxide-semiconductor field effect transistor of claim 1 in which said shield region has an ion concentration in the range of about 5×10 13 to about 5×10 15 cm -3 .

Claim 4

A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a body region of a second conductivity type; and a drain region of said first conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said body region into said drain region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said drain region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 5

A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a body region of a second conductivity type; and a drain region of said first conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said body region into said drain region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said drain region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 6

The metal-oxide-semiconductor field effect transistor of claim 3 in which said shield region has an ion concentration in the range of about 1×10 16 to about 1×10 20 cm -3 .

Claim 7

The metal-oxide-semiconductor field effect transistor of claim 2 or 4 wherein said body region includes a well of relatively heavily doped material.

Claim 8

The metal-oxide-semiconductor field effect transistor of claim 5 wherein the bottom of said well is located at a level 0.5 μm or more below the bottom of said trench.

Claim 9

The metal-oxide-semiconductor field effect transistor of claim 5 wherein the bottom of said well is located at a level higher than 0.5 μm below the bottom of said trench.

Claim 10

The metal-oxide-semiconductor field effect transistor of claim 2 or 4 wherein said gate partially surrounds a dielectric region.

Claim 11

The metal-oxide-semiconductor field effect transistor of claim 8 wherein said dielectric region is selected from the group consisting of borophosphosilicate glass, phosphosilicate glass or a low temperature oxide.

Claim 12

A semiconductor chip including a plurality of the transistors claimed in claims 2 or 4 wherein said trenches form a lattice configuration.

Claim 13

The semiconductor chip of claim 10 wherein said trenches form an orthogonal lattice.

Claim 14

The semiconductor chip of claim 10 wherein said trenches form a hexagonal lattice.

Claim 15

A semiconductor chip including a plurality of the transistors claimed in claims 2 or 4 wherein said trenches form a series of substantially parallel lines.

Claim 16

A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a body region of a second conductivity type; a drift region of said first conductivity type; and a drain region of said first conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said body region into said drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said drift region and said insulating layer and adjacent to said corner, said shield region being of said first conductivity type and being doped to a lesser degree than said drift region, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 17

A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a body region of a second conductivity type; a drift region of said first conductivity type; and a drain region of said first conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said body region into said drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said drift region and said insulating layer and adjacent to said corner, said shield region being of said first conductivity type and being doped to a lesser degree than said drift region, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 18

A metal-oxide-semiconductor field effect transistor of claim 14 in which said shield region has an ion concentration in the range of about 5×10 13 to about 5×10 15 cm -3 .

Claim 19

A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a body region of a second conductivity type; a drift region of said first conductivity type; and a drain region of said first conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said body region into said drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said drift region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 20

A metal-oxide-semiconductor field effect transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a body region of a second conductivity type; a drift region of said first conductivity type; and a drain region of said first conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said body region into said drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said drift region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 21

The metal-oxide-semiconductor field effect transistor of claim 16 in which said shield region has an ion concentration in the range of about 1×10 16 to about 1×10 20 cm -3 .

Claim 22

The metal-oxide-semiconductor field effect transistor of claims 15 or 17 wherein said body region includes a well of relatively heavily doped material.

Claim 23

The metal-oxide-semiconductor field effect transistor of claim 18 wherein the bottom of said well is located at a level 0.5 μm or more below the bottom of said trench.

Claim 24

The metal-oxide-semiconductor field effect transistor of claim 18 wherein the bottom of said sell is located at a level higher than 0.5 μm below the bottom of said trench.

Claim 25

The metal-oxide-semiconductor field effect transistor of claims 15 or 17 wherein said gate partially surrounds a dielectric region.

Claim 26

The metal-oxide-semiconductor field effect transistor of claim 21 wherein said dielectric region is selected from the group consisting of borophosphosilicate glass, phosphosilicate glass or a low temperature oxide.

Claim 27

A semiconductor chip including a plurality of the transistors claimed in claims 15 or 17 wherein said trenches form a lattice configuration.

Claim 28

The semiconductor chip of claim 23 wherein said trenches form an orthogonal lattice.

Claim 29

The semiconductor chip of claim 23 wherein said trenches form a hexagonal lattice.

Claim 30

A semiconductor chip including a plurality of the transistors claimed in claims 15 or 17 wherein said trenches form a series of substantially parallel lines.

Claim 31

An insulated gate bipolar transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a collector/body region of a second conductivity type; a base/drift region of said first conductivity type; a drain region; and an emitter of said second conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said collector/body region into said base/drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said base/drift region and said insulating layer and adjacent to said corner, said shield region being of said first conductivity type and being doped to a lesser degree than said base/drift region, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 32

An insulated gate bipolar transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a collector/body region of a second conductivity type; a base/drift region of said first conductivity type; a drain region; and an emitter of said second conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said collector/body region into said base/drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said base/drift region and said insulating layer and adjacent to said corner, said shield region being of said first conductivity type and being doped to a lesser degree than said base/drift region, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 33

The insulating gate bipolar transistor of claim 27 in which said shield region has an ion concentration in the range of about 5×10 -- to about 5×10 15 cm -3 .

Claim 34

An insulated gate bipolar transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a collector/body region of a second conductivity type; a base/drift region of said first conductivity type; a drain region; and an emitter of said second conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said collector/body region into said base/drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said base/drift region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 35

An insulated gate bipolar transistor in a grooved or trench configuration and comprising the following regions in succession: a source region of a first conductivity type; a collector/body region of a second conductivity type; a base/drift region of said first conductivity type; a drain region; and an emitter of said second conductivity type; and additionally comprising a gate formed in a trench or groove, said trench or groove extending through said collector/body region into said base/drift region, said gate bordered by an insulating layer, said insulating layer having a boundary, and said boundary including a corner; and a shield region bounded by said base/drift region and said insulating layer and adjacent to said corner, said shield region being of said second conductivity type, said shield region operating to inhibit voltage breakdown at or near said corner.

Claim 36

The insulated gate bipolar transistor of claim 29 in which said shield region has an ion concentration in the range of about 1×10 16 to about 1×10 20 cm -3 .

Claim 37

The insulated gate bipolar transistor of claims 28 or 30 wherein said collector/body region includes a well of relatively heavily doped material.

Claim 38

The insulated gate bipolar transistor of claim 31 wherein the bottom of said well is located at a level 0.5 μm or more below the bottom of said trench.

Claim 39

The insulated gate bipolar transistor of claim 31 wherein the bottom of said well is located at a level higher than 0.5 μm below the bottom of said trench.

Claim 40

The insulated gate bipolar transistor of claims 28 or 30 wherein said gate partially surrounds a dielectric region.

Claim 41

The insulated gate bipolar transistor of claim 34 wherein said dielectric region is selected from the group consisting of borophosphosilicate glass, phosphosilicate glass or a low temperature oxide.

Claim 42

A semiconductor chip including a plurality of the transistors claimed in claims 28 or 30 wherein said trenches form a lattice configuration.

Claim 43

The semiconductor chip of claim 36 wherein said trenches form an orthogonal lattice.

Claim 44

The semiconductor chip of claim 36 wherein said trenches form a hexagonal lattice.

Claim 45

A semiconductor chip including a plurality of the transistors claimed in claims 28 or 30 wherein said trenches form a series of substantially parallel lines.