MOSFET-gated bipolar transistors and thyristors with both turn-on and turn-off capability having single-polarity gate input signal

Claim 2

A MOSFET-gated thyristor integrated device having single polarity turn-on and turn-off control, said integrated device comprising: a four-layer semiconductor switching device including, in order, an anode region layer of P conductivity type, a first base region layer of N conductivity type, a second base region layer of P conductivity type, and a cathode region layer of N conductivity type; an enhancement mode MOSFET having a gate electrode and having one main electrode connected to said cathode region layer and another main electrode connected to said first base region layer for biasing said switching device into conduction when said enhancement mode MOSFET is conducting; and a depletion mode MOSFET having a gate electrode and having one main electrode connected to said second base region layer and another main electrode connected to said cathode region layer for turning off said switching device when said depletion mode MOSFET is conducting.

Claim 3

A MOSFET-gated thyristor device in accordance with claim 1, which further comprises an electrical connection between said MOSFET gate electrodes.

Claim 4

A MOSFET-gated thyristor device in accordance with claim 1, wherein said enhancement mode MOSFET has a channel of N conductivity type, and said depletion mode MOSFET has a channel of P conductivity type.

Claim 5

A MOSFET-gated thyristor device in accordance with claim 2, wherein said enhancement mode MOSFET has a channel of N conductivity type, and said depletion mode MOSFET has a channel of P conductivity type.

Claim 6

A MOSFET-gated thyristor integrated device having a single input polarity turn-on and turn-off control, said integrated device comprising: a four-layer semiconductor switching device having a principal surface and including, in order, an anode region layer located farthest from said principal surface and of P conductivity type; a first base region layer of N conductivity type terminating at said principal surface and defining a first PN junction with said anode region layer; a second base region layer of P conductivity type formed within said first base region and defining a second PN junction within said first base region, said second base region being of limited lateral extent and having a periphery terminating at said principal surface; and a cathode region layer of N conductivity type formed within said second base region and defining a third PN junction with said second base region, said cathode region being of limited lateral extent and having a periphery terminating at said principal surface; a first termination region of N conductivity type formed within said second base region as an extension of said cathode region, said first termination region extending to said principal surface and spaced from said first base region such that at said principal surface a portion of said second base region exists as a band of P conductivity type between said first termination region and said first base region; a first MOSFET gate insulating layer disposed on said principal surface over at least a portion of said band, and a first MOSFET conductive gate electrode disposed on said first MOSFET gate insulating layer at least laterally over a portion of said first band, such that a first MOSFET device is defined of the enhancement mode type, arranged to establish a channel of N conductivity type extending between said first base region and said first termination region for turning on said switching device when gate voltage is applied; a second termination region of P conductivity type formed within said cathode region, said second termination region extending to said principal surface and spaced from said second base region such that at said principal surface a gap is defined between said second termination region and said second base region, a second MOSFET depletion mode channel region of P conductivity type formed at said principal surface in said gap so as to fill said gap and connect said second termination region and said second base region; a second MOSFET gate insulating layer disposed on said principal surface over at least a portion of said second MOSFET depletion mode channel, and a second MOSFET conductive gate electrode disposed on said second MOSFET gate insulating layer at least laterally over a portion of said depletion mode channel region; and an ohmic connection between said second termination region and said cathode region such that, when conducting, the channel of said second MOSFET device electrically connects said switching device cathode and second base regions for turning off said switching device.

Claim 7

A MOSFET-gated thyristor integrated device having a single input polarity turn-on and turn-off control, said integrated device comprising: a four-layer semiconductor switching device having a principal surface and including, in order, an anode region layer located farthest from said principal surface and of P conductivity type; a first base region layer of N conductivity type terminating at said principal surface and defining a first PN junction with said anode region layer; a second base region layer of P conductivity type formed within said first base region and defining a second PN junction within said first base region, said second base region being of limited lateral extent and having a periphery terminating at said principal surface; and a cathode region layer of N conductivity type formed within said second base region and defining a third PN junction with said second base region, said cathode region being of limited lateral extent and having a periphery terminating at said principal surface; a first termination region of N conductivity type formed within said second base region as an extension of said cathode region, said first termination region extending to said principal surface and spaced from said first base region such that at said principal surface a portion of said second base region exists as a band of P conductivity type between said first termination region and said first base region; a first MOSFET gate insulating layer disposed on said principal surface over at least a portion of said band, and a first MOSFET conductive gate electrode disposed on said first MOSFET gate insulating layer at least laterally over a portion of said first band, such that a first MOSFET device is defined of the enhancement mode type, arranged to establish a channel of N conductivity type extending between said first base region and said first termination region for turning on said switching device when gate voltage is applied; a second termination region of P conductivity type formed within said cathode region, said second termination region extending to said principal surface and spaced from said second base region such that at said principal surface a gap is defined between said second termination region and said second base region, a second MOSFET depletion mode channel region of P conductivity type formed at said principal surface in said gap so as to fill said gap and connect said second termination region and said second base region; a second MOSFET gate insulating layer disposed on said principal surface over at least a portion of said second MOSFET depletion mode channel, and a second MOSFET conductive gate electrode disposed on said second MOSFET gate insulating layer at least laterally over a portion of said depletion mode channel region; and an ohmic connection between said second termination region and said cathode region such that, when conducting, the channel of said second MOSFET device electrically connects said switching device cathode and second base regions for turning off said switching device.

Claim 8

A MOSFET-gate thyristor device in accordance with claim 5, wherein said second MOSFET depletion mode channel region comprises an ion-implanted region.

Claim 9

A MOSFET-gated thyristor in accordance with claim 5, wherein said second termination region is formed within said cathode region.

Claim 10

A MOSFET-gated thyristor in accordance with claim 5, wherein said second termination region is formed within said first base region.

Claim 11

A MOSFET-gated thyristor in accordance with claim 5, which further comprises an electrical connection between said MOSFET gate electrodes.

Claim 12

A MOSFET-gated thyristor in accordance with claim 7, which further comprises an electrical connection between said MOSFET gate electrodes.

Claim 13

A MOSFET-gated thyristor in accordance with claim 8, which further comprises an electrical connection between said MOSFET gate electrodes.

Claim 14

A MOSFET-gated thyristor integrated device having a single polarity turn-on and turn-off control, said integrated device comprising: a four-layer semiconductor switching device having a principal surface and including, in order, an anode region layer located farthest from said principal surface and of P conductivity type; a first base region layer of N conductivity type terminating at said principal surface and defining a first PN junction with said anode region layer; a second base region layer of P conductivity type formed within said first base region and defining a second PN junction with said first base region, said second base region being of limited lateral extent and having a periphery terminating at said principal surface; and a cathode region layer of N conductivity type formed within said second base region and defining a third PN junction with said second base region, said cathode region being of limited lateral extend and having a periphery terminating at said principal surface; a first MOSFET channel surface; a first termination region of N conductivity type formed within said second base region as an extension of said cathode region, said first termination region extending to said principal surface and spaced from, at the first MOSFET channel surface, said first base region such that at said first MOSFET channel surface a portion of said second base region exists as a band of P conductivity type between said first termination region and said first base region; a first MOSFET gate insulating layer disposed on said first MOSFET channel surface over at least a portion of said band, and a first MOSFET conductive gate electrode disposed on said first MOSFET gate insulating layer at least over a portion of said first band, such that a first MOSFET device is defined of the enhancement mode type, arranged to establish a channel of N conductivity type extending between said first base region and said first termination region for turning on said switching device when gate voltage is applied; a second MOSFET channel surface; a second termination region of P conductivity type formed within said cathode region, said second termination region extending to said principal surface and spaced from said second base region such that at said second MOSFET channel surface a gap is defined between said second termination region and said second base region, a second MOSFET depletion mode channel region of P conductivity type formed at said second MOSFET channel surface in said gap so as to fill said gap and connect said second termination region and said second base region; a second MOSFET gate insulating layer disposed on said second MOSFET channel surface over at least a portion of said second MOSFET depletion mode channel, and a second MOSFET conductive gate electrode disposed on said second MOSFET gate insulating layer at least over a portion of said depletion mode channel region; and an ohmic connection between said second termination region and said cathode region such that, when conducting, the channel of said second MOSFET device electrically connects said switching device cathode and second base regions for turning off said switching device.

Claim 15

A MOSFET-gated thyristor integrated device having a single polarity turn-on and turn-off control, said integrated device comprising: a four-layer semiconductor switching device having a principal surface and including, in order, an anode region layer located farthest from said principal surface and of P conductivity type; a first base region layer of N conductivity type terminating at said principal surface and defining a first PN junction with said anode region layer; a second base region layer of P conductivity type formed within said first base region and defining a second PN junction with said first base region, said second base region being of limited lateral extent and having a periphery terminating at said principal surface; and a cathode region layer of N conductivity type formed within said second base region and defining a third PN junction with said second base region, said cathode region being of limited lateral extend and having a periphery terminating at said principal surface; a first MOSFET channel surface; a first termination region of N conductivity type formed within said second base region as an extension of said cathode region, said first termination region extending to said principal surface and spaced from, at the first MOSFET channel surface, said first base region such that at said first MOSFET channel surface a portion of said second base region exists as a band of P conductivity type between said first termination region and said first base region; a first MOSFET gate insulating layer disposed on said first MOSFET channel surface over at least a portion of said band, and a first MOSFET conductive gate electrode disposed on said first MOSFET gate insulating layer at least over a portion of said first band, such that a first MOSFET device is defined of the enhancement mode type, arranged to establish a channel of N conductivity type extending between said first base region and said first termination region for turning on said switching device when gate voltage is applied; a second MOSFET channel surface; a second termination region of P conductivity type formed within said cathode region, said second termination region extending to said principal surface and spaced from said second base region such that at said second MOSFET channel surface a gap is defined between said second termination region and said second base region, a second MOSFET depletion mode channel region of P conductivity type formed at said second MOSFET channel surface in said gap so as to fill said gap and connect said second termination region and said second base region; a second MOSFET gate insulating layer disposed on said second MOSFET channel surface over at least a portion of said second MOSFET depletion mode channel, and a second MOSFET conductive gate electrode disposed on said second MOSFET gate insulating layer at least over a portion of said depletion mode channel region; and an ohmic connection between said second termination region and said cathode region such that, when conducting, the channel of said second MOSFET device electrically connects said switching device cathode and second base regions for turning off said switching device.

Claim 16

A MOSFET-gated thyristor device in accordance with claim 12, wherein said second MOSFET depletion mode channel region comprises an ion-implanted region.

Claim 17

A MOSFET-gate thyristor in accordance with claim 8, which further comprises an electrical connection between said MOSFET gate electrodes.