High-density V-groove MOS-controlled thyristors, insulated-gate transistors, and MOSFETs, and methods for fabrication

Claim 2

A process for manufacturing an insulated-gate semiconductor device of V-groove configuration, said process comprising: providing a semiconductor wafer having a principal surface and including at least first, second and third successive contiguous layers, the first layer being of one conductivity type and extending to the principal surface and the second layer being of opposite conductivity type; forming on the principal surface a layer of a material constituting a first mask; forming at least one elongated opening in the first mask layer to define the ultimate location of a V-groove; introducing into the first semiconductor layer through each openings in the first mask dopant impurities appropriate to form at the principal surface a channel-terminating electrode region of the opposite conductivity type, and at least laterally diffusing the impurities part way under the mask to form the channel-terminating electrode region while leaving a portion of the first layer extending to the principal surface; applying an etchant through each opening in the first mask so as to form below each opening a V-groove extending from the principal surface through the first semiconductor layer and part way into the second semiconductor layer; forming a gate insulating layer on the sides of the V-groove; forming a gate electrode on the gate insulating layer; and providing an upper main electrode in electrical contact with the channel-terminating electrode region and with the extending portion of the first semiconductor layer.

Claim 3

A process in accordance with claim 1, wherein the step of providing a semiconductor wafer includes forming, as a portion of the first semiconductor layer, a relatively more heavily doped layer of the one conductivity type immediately adjacent the principal surface.

Claim 4

A process in accordance with claim 1, wherein the third layer of the semiconductor wafer is of one conductivity type and wherein the process further comprises providing a lower main electrode in electrical contact with the third layer.

Claim 5

A process in accordance with claim 2, wherein the third layer of the semiconductor wafer is of one conductivity type and wherein the process further comprises providing a lower main electrode in electrical contact with the third layer.

Claim 6

A process in accordance with claim 2, wherein the semiconductor wafer includes a fourth layer contiguous with the third layer, the third and fourth layers being of the one and opposite conductivity types, respectively, and wherein the process further comprises providing a lower main electrode in electrical contact with the fourth layer.

Claim 7

A process in accordance with claim 1, wherein the step of forming on the principal surface a first mask layer comprises forming a silicon nitride mask layer.

Claim 8

A process in accordance with claim 6, wherein the step of forming a gate electrode comprises: forming a highly doped polysilicon layer over the entire wafer; providing a second mask over the polysilicon layer; etching through the polysilicon layer to open upper main electrode contact windows to form gate electrode isolation insulation; and opening remote gate electrode contact windows through the gate electrode isolation insulation.

Claim 9

A process in accordance with claim 7, wherein the step of providing an upper main electrode comprises, subsequent to oxidizing the exposed surfaces of the polysilicon layer, removing the silicon nitride mask to expose the channel-terminating electrode region and the extending portion of the first semiconductor layer, whereby the silicon nitride mask layer protects the channel-terminating electrode region and the extending portion of the first semiconductor layer from oxidation.

Claim 10

A process in accordance with claim 7, wherein the upper main electrode contact windows defined by the second mask are parallel to and substantially co-extensive with the V-groove.

Claim 11

A process in accordance with claim 8, wherein a plurality of parallel elongated openings are formed in the first mask and wherein said etchant is applied through each of said openings, such that a plurality of V-grooves are formed in the semiconductor wafer during the step of applying said etchant through each of said openings and such that between each adjacent pair of V-grooves a pair of channel-terminating electrode regions are formed during the step of introducing dopant impurities through each of said openings in the first mask, the pair of channel-terminating upper electrode regions being separated by an intermediate extending portion of the first semiconductor layer.

Claim 12

A process in accordance with claim 10 including the step of forming upper main electrode contact windows at generally right angles to the V-grooves and extending far enough to span a pair of channel-terminating upper electrode regions and the intermediate extending portion.

Claim 13

A process in accordance with claim 1, wherein the step of forming on the principal surface a first mask layer comprises forming a refractory metal silicide layer which remains in the completed device to form the upper main electrode.

Claim 14

A process in accordance with claim 12, wherein the step of providing an upper main electrode comprises oxidizing the exposed surfaces of the refractory metal silicide layer including sidewalls of the elongated opening in the first mask to form upper main electrode isolation insulation.

Claim 15

A metal-oxide-semiconductor turn-off thyristor of V-groove configuration comprising: a semiconductor body having first and second opposed principal surfaces and including first, second, third and fourth successive layers of alternate conductivity type, said first and third layers being of one conductivity type and said second and fourth layers being of opposite conductivity type; said first layer being adjacent said first principal surface and including two portions of differing doping concentration, one of said portions having a relatively higher doping concentration being immediately adjacent said first principal surface, and the other of said portions having a relatively lower doping concentration being separated from said first principal surface by said one portion; a V-groove extending from said first principal surface through said first layer such that at least said other portion of said first layer abuts a side of said V-groove along a lower portion of said V-groove; a channel-terminating electrode region of the opposite conductivity type formed within said first layer immediately adjacent an upper portion of said V-groove and extending to both said first principal surface and said V-groove upper portion, said channel-terminating electrode region and said second layer together defining the length of a channel region therebetween and within said other of said first layer portions; a first main terminal electrode in electrical contact at said first principal surface with said one of said first layer portions and with said channel-terminating upper electrode region; a second main terminal electrode in electrical contact at said second principal surface with said fourth layer; and an insulated gate electrode overlying said channel region and configured such that an inversion channel electrically connecting said channel-terminating electrode region and said second layer is induced in said channel region upon application to said gate electrode of a bias voltage having predetermined polarity and magnitude.

Claim 16

A metal-oxide-semiconductor turn-off thyristor of V-groove configuration comprising: a semiconductor body having first and second opposed principal surfaces and including first, second, third and fourth successive layers of alternate conductivity type, said first and third layers being of one conductivity type and said second and fourth layers being of opposite conductivity type; said first layer being adjacent said first principal surface and including two portions of differing doping concentration, one of said portions having a relatively higher doping concentration being immediately adjacent said first principal surface, and the other of said portions having a relatively lower doping concentration being separated from said first principal surface by said one portion; a V-groove extending from said first principal surface through said first layer such that at least said other portion of said first layer abuts a side of said V-groove along a lower portion of said V-groove; a channel-terminating electrode region of the opposite conductivity type formed within said first layer immediately adjacent an upper portion of said V-groove and extending to both said first principal surface and said V-groove upper portion, said channel-terminating electrode region and said second layer together defining the length of a channel region therebetween and within said other of said first layer portions; a first main terminal electrode in electrical contact at said first principal surface with said one of said first layer portions and with said channel-terminating upper electrode region; a second main terminal electrode in electrical contact at said second principal surface with said fourth layer; and an insulated gate electrode overlying said channel region and configured such that an inversion channel electrically connecting said channel-terminating electrode region and said second layer is induced in said channel region upon application to said gate electrode of a bias voltage having predetermined polarity and magnitude.

Claim 17

The thyristor of claim 14 wherein said first main terminal electrode comprises metal silicide.

Claim 18

An insulated-gate transistor of V-groove configuration comprising: a semiconductor body having first and second opposed principal surfaces and including first, second and third successive layers of alternate conductivity type, said first and third layers being of one conductivity type and said second layer being of opposite conductivity type; said first layer being adjacent said first principal surface and including two portions of differing doping concentration, one of said portions having a relatively higher doping concentration and being immediately adjacent said first principal surface, and the other of said portions having a relatively lower doping concentration and being separated from said first principal surface by said one portion; a V-groove extending from said first principal surface through said first layer such that at least said other portion of said first layer abuts a side of said V-groove along a lower portion of said V-groove; a channel-terminating electrode region of the opposite conductivity type formed within said first layer immediately adjacent an upper portion of said V-groove and abutting both said first principal surface and said V-groove upper portion, said channel-terminating electrode region and said second layer together defining the length of a channel region therebetween and within said other of said first layer portions; a first main terminal electrode in electrical contact at said first principal surface with said one of said first layer portions and with said channel-terminating electrode region; a second main terminal electrode in electrical contact at said second principal surface with said third layer; and an insulated gate electrode overlying said channel region and configured such that an inversion channel electrically connecting said channel-terminating electrode region and said second layer is induced in said channel region upon application to said gate electrode of a bias voltage having predetermined polarity and magnitude.

Claim 19

An insulated-gate transistor of V-groove configuration comprising: a semiconductor body having first and second opposed principal surfaces and including first, second and third successive layers of alternate conductivity type, said first and third layers being of one conductivity type and said second layer being of opposite conductivity type; said first layer being adjacent said first principal surface and including two portions of differing doping concentration, one of said portions having a relatively higher doping concentration and being immediately adjacent said first principal surface, and the other of said portions having a relatively lower doping concentration and being separated from said first principal surface by said one portion; a V-groove extending from said first principal surface through said first layer such that at least said other portion of said first layer abuts a side of said V-groove along a lower portion of said V-groove; a channel-terminating electrode region of the opposite conductivity type formed within said first layer immediately adjacent an upper portion of said V-groove and abutting both said first principal surface and said V-groove upper portion, said channel-terminating electrode region and said second layer together defining the length of a channel region therebetween and within said other of said first layer portions; a first main terminal electrode in electrical contact at said first principal surface with said one of said first layer portions and with said channel-terminating electrode region; a second main terminal electrode in electrical contact at said second principal surface with said third layer; and an insulated gate electrode overlying said channel region and configured such that an inversion channel electrically connecting said channel-terminating electrode region and said second layer is induced in said channel region upon application to said gate electrode of a bias voltage having predetermined polarity and magnitude.

Claim 20

The transistor of claim 16 wherein said first main terminal electrode comprises metal silicide.

Claim 21

A MOS field-effect transistor of V-groove configuration comprising: a semiconductor body having first and second opposed principal surfaces and including first, second and third successive layers, said first layer being of one conductivity type and said second and third layers being of opposite conductivity type; said first layer being adjacent said first principal surface and including two portions of differing doping concentration, one of said portions having a relatively higher doping concentration and being immediately adjacent said first principal surface, and the other of said portions having a relatively lower doping concentration and being separated from said first principal surface by said one portion; a V-groove extending from said first principal surface through said first layer such that at least said other portion of said first layer abuts a side of said V-groove along a lower portion of said V-groove; a channel-terminating electrode region of the opposite conductivity type formed within said first layer immediately adjacent an upper portion of said V-groove and abutting both said first principal surface and said V-groove upper portion, said channel-terminating electrode region and said second layer together defining the length of a channel region therebetween and within said other of said first layer portions; a first main terminal electrode in electrical contact at said first principal surface with said one of said first layer portions and with said channel-terminating electrode region; a second main terminal electrode in electrical contact at said second principal surface with said third layer; and an insulated gate electrode overlying said channel region and configured such that an inversion channel electrically connecting said channel-terminating electrode region and said second layer is induced in said channel region upon application to said gate electrode of a bias voltage having predetermined polarity and magnitude.

Claim 22

A MOS field-effect transistor of V-groove configuration comprising: a semiconductor body having first and second opposed principal surfaces and including first, second and third successive layers, said first layer being of one conductivity type and said second and third layers being of opposite conductivity type; said first layer being adjacent said first principal surface and including two portions of differing doping concentration, one of said portions having a relatively higher doping concentration and being immediately adjacent said first principal surface, and the other of said portions having a relatively lower doping concentration and being separated from said first principal surface by said one portion; a V-groove extending from said first principal surface through said first layer such that at least said other portion of said first layer abuts a side of said V-groove along a lower portion of said V-groove; a channel-terminating electrode region of the opposite conductivity type formed within said first layer immediately adjacent an upper portion of said V-groove and abutting both said first principal surface and said V-groove upper portion, said channel-terminating electrode region and said second layer together defining the length of a channel region therebetween and within said other of said first layer portions; a first main terminal electrode in electrical contact at said first principal surface with said one of said first layer portions and with said channel-terminating electrode region; a second main terminal electrode in electrical contact at said second principal surface with said third layer; and an insulated gate electrode overlying said channel region and configured such that an inversion channel electrically connecting said channel-terminating electrode region and said second layer is induced in said channel region upon application to said gate electrode of a bias voltage having predetermined polarity and magnitude.

Claim 23

The transistor of claim 18 wherein said first main terminal electrode comprises metal silicide.