Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor

Claim 2

A semiconductor processing method of forming a contact pedestal comprising the following steps: providing a node location to which electrical connection is to be made; providing insulating dielectric material over the node location; etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base; providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location; filling the contact opening to the node location with electrically conductive material; rendering the sidewall spacer electrically conductive; and etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces.

Claim 3

The semiconductor processing method of forming a contact pedestal of claim 1 wherein the spacer layer is provided to be electrically conductive prior to the anisotropic etching thereby rendering the spacer to be electrically conductive immediately upon its formation.

Claim 4

The semiconductor processing method of forming a contact pedestal of claim 1 wherein the spacer layer is not provided to be electrically conductive prior to the anisotropic etching, the spacer being rendered electrically conductive after the anisotropic etching.

Claim 5

The semiconductor processing method of forming a contact pedestal of claim 1 wherein the insulating dielectric material includes an outermost surface, the outermost surface being substantially unplanarized prior to the etching step to form the pedestal.

Claim 6

The semiconductor processing method of forming a contact pedestal of claim 1 wherein the insulating dielectric material includes an outermost surface, the outermost surface being substantially planar prior to the etching step to form the pedestal.

Claim 7

The semiconductor processing method of forming a contact pedestal of claim 1 wherein the insulating dielectric material includes an outermost surface, the outermost surface being substantially unplanarized prior to the etching step to form the pedestal, an unplanarized masking layer being provided over the unplanarized insulating dielectric material outermost surface prior to the etching step to form the pedestal.

Claim 8

The semiconductor processing method of forming a contact pedestal of claim 1 further comprising: providing a capacitor container opening and a second layer of electrically conductive material over the insulating dielectric layer and to within the capacitor container opening to a thickness which less than completely fills the capacitor container opening; and the etching step to form the pedestal also including etching the second layer of conductive material to define an isolated capacitor storage node plate within the capacitor container opening.

Claim 9

The semiconductor processing method of forming a contact pedestal of claim 1 further comprising: providing a second node location and a second contact opening into the insulating dielectric layer over the second node location, the second contact opening being insufficiently deep to outwardly expose the second node location, the second contact opening having a second base; the spacer layer also being provided within the second contact opening and the anisotropic etching thereof providing a second spacer within the second contact opening; after forming the second sidewall spacer, etching through the second contact opening base to outwardly expose the second node location; filling the second contact opening to the second node location with the electrically conductive material; before the etching step to form the pedestal, etching the insulating dielectric material and the conductive material filling the second contact opening to form a capacitor container opening over the second node location and a pillar of conductive material extending between the capacitor container opening and the second node location; providing a second layer of electrically conductive material over the insulating dielectric layer and to within the capacitor container opening to a thickness which less than completely fills the capacitor container opening; and the etching step to form the pedestal also including etching the second layer of conductive material to define an isolated capacitor storage node plate within the capacitor container opening.

Claim 10

The semiconductor processing method of forming a contact pedestal of claim 8 wherein the etching to form the capacitor container contact opening is conducted to etch the insulating dielectric material and the conductive material filling the second contact opening at substantially the same rate.

Claim 11

A semiconductor processing method of forming a contact pedestal comprising the following steps: providing a pair of wordlines having a node location therebetween to which electrical connection is to be made; providing insulating dielectric material over the pair of wordlines and the node location; etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location between the pair of wordlines, the contact opening having a base positioned elevationally outward of conductive portions of the pair of wordlines; providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location between the pair of wordlines; filling the contact opening to the node location with electrically conductive material; rendering the sidewall spacer electrically conductive; and etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces.

Claim 12

A semiconductor processing method of forming a contact pedestal comprising the following steps: providing a pair of wordlines having a node location therebetween to which electrical connection is to be made; providing insulating dielectric material over the pair of wordlines and the node location; etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location between the pair of wordlines, the contact opening having a base positioned elevationally outward of conductive portions of the pair of wordlines; providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; anisotropically etching the spacer layer to form a sidewall spacer within the contact opening; after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location between the pair of wordlines; filling the contact opening to the node location with electrically conductive material; rendering the sidewall spacer electrically conductive; and etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces.

Claim 13

The semiconductor processing method of forming a contact pedestal of claim 10 wherein the spacer layer is provided to be electrically conductive prior to the anisotropic etching thereby rendering the spacer to be electrically conductive immediately upon its formation.

Claim 14

The semiconductor processing method of forming a contact pedestal of claim 10 wherein the spacer layer is not provided to be electrically conductive prior to the anisotropic etching, the spacer being rendered electrically conductive after the anisotropic etching.

Claim 15

The semiconductor processing method of forming a contact pedestal of claim 10 wherein the insulating dielectric material includes an outermost surface, the outermost surface being substantially unplanarized prior to the etching step to form the pedestal.

Claim 16

The semiconductor processing method of forming a contact pedestal of claim 10 further comprising providing wordlines with etch stop caps prior to providing said insulating dielectric material, the etch stop caps being of a different material than said dielectric material, the method further comprising planarize etching said dielectric material to the etch stop caps prior to etching the contact opening.

Claim 17

The semiconductor processing method of forming a contact pedestal of claim 10 wherein the insulating dielectric material comprises etch stop caps over wordlines, the method further comprising planarize etching dielectric material to the etch stop caps prior to etching the contact opening.

Claim 18

The semiconductor processing method of forming a contact pedestal of claim 10 wherein the insulating dielectric material includes an outermost surface, the outermost surface being substantially unplanarized prior to the etching step to form the pedestal, an unplanarized masking layer being provided over the unplanarized insulating dielectric material outermost surface prior to the etching step to form the pedestal.

Claim 19

The semiconductor processing method of forming a contact pedestal of claim 10 further comprising: providing a capacitor container opening and a second layer of electrically conductive material over the insulating dielectric layer and to within the capacitor opening to a thickness which less than completely fills the capacitor container opening; and the etching step to form the pedestal also including etching the second layer of conductive material to define an isolated capacitor storage node plate within the capacitor container opening.

Claim 20

The semiconductor processing method of forming a contact pedestal of claim 10 further comprising: providing a second node location and a second contact opening into the insulating dielectric layer over the second node location, the second contact opening being insufficiently deep to outwardly expose the second node location, the second contact opening having a second base; the spacer layer also being provided within the second contact opening and the anisotropic etching thereof providing a second spacer within the second contact opening; after forming the second sidewall spacer, etching through the second contact opening base to outwardly expose the second node location; filling the second contact opening to the second node location with the electrically conductive material; before the etching step to form the pedestal, etching the insulating dielectric material and the conductive material filling the second contact opening to form a capacitor container opening over the second node location and a pillar of conductive material extending between the capacitor container opening and the second node location; providing a second layer of electrically conductive material over the insulating dielectric layer and to within the capacitor container opening to a thickness which less than completely fills the capacitor container opening; and the etching step to form the pedestal also including etching the second layer of conductive material to define an isolated capacitor storage node plate within the capacitor container opening.

Claim 21

The semiconductor processing method of forming a contact pedestal of claim 18 wherein the etching to form the capacitor container contact opening is conducted to etch the insulating dielectric material and the conductive material filling the second contact opening at substantially the same rate.

Claim 22

A semiconductor processing method of forming a contact pedestal comprising the following steps: providing a pair of wordlines having a node location therebetween to which electrical connection is to be made; providing insulating dielectric material over the pair of wordlines and the node location; etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location between the pair of wordlines, tire contact opening having a base positioned elevationally outward of conductive portions of the pair of wordlines; providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; anisotropically etching the spacer layer to form a sidewall spacer within the contact opening and to outwardly expose the insulating dielectric material over the pair of wordlines; after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location between the pair of wordlines, the step of etching through the contact opening base also etching insulating dielectric material over the pair of wordlines but to a degree insufficient to outwardly expose the pair of wordlines; filling the contact opening to the node location with electrically conductive material; rendering the sidewall spacer electrically conductive; and etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces.

Claim 23

A semiconductor processing method of forming a contact pedestal comprising the following steps: providing a pair of wordlines having a node location therebetween to which electrical connection is to be made; providing insulating dielectric material over the pair of wordlines and the node location; etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location between the pair of wordlines, tire contact opening having a base positioned elevationally outward of conductive portions of the pair of wordlines; providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; anisotropically etching the spacer layer to form a sidewall spacer within the contact opening and to outwardly expose the insulating dielectric material over the pair of wordlines; after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location between the pair of wordlines, the step of etching through the contact opening base also etching insulating dielectric material over the pair of wordlines but to a degree insufficient to outwardly expose the pair of wordlines; filling the contact opening to the node location with electrically conductive material; rendering the sidewall spacer electrically conductive; and etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces.

Claim 24

The semiconductor processing method of forming a contact pedestal of claim 20 wherein the spacer layer is provided to be electrically conductive prior to the anisotropic etching thereby rendering the spacer to be electrically conductive immediately upon its formation.

Claim 25

The semiconductor processing method of forming a contact pedestal of claim 20 wherein the spacer layer is not provided to be electrically conductive prior to the anisotropic etching, the spacer being rendered electrically conductive after the anisotropic etching.

Claim 26

The semiconductor processing method of forming a contact pedestal of claim 20 wherein the insulating dielectric material includes an outermost surface, the outermost surface being substantially unplanarized prior to the etching step to form the pedestal.

Claim 27

The semiconductor processing method of forming a contact pedestal of claim 20 wherein the quantity of insulating material etched over the pair of wordlines during the step of etching through the contact opening base is greater than or equal to at least about 1.3 times the distance between the contact base and the node location.

Claim 28

The semiconductor processing method of forming a contact pedestal of claim 20 wherein the quantity of insulating material etched over the pair of wordlines during the step of etching through the contact opening base is equal to from about 1.3 to 1.5 times the distance between the contact base and the node location.

Claim 29

A semiconductor processing method of forming a contact pedestal comprising the following steps: providing a conductive line having a node location adjacent thereto to which electrical connection is to be made; providing insulating dielectric material over the conductive line and the node location; etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base positioned elevationally outward of the conductive line; providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; anisotropically etching the spacer layer to form a sidewall spacer within the contact opening and to outwardly expose the insulating dielectric material over the conductive line; after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location, the step of etching through the contact opening base also etching insulating dielectric material over the conductive line but to a degree insufficient to outwardly expose the conductive line; filling the contact opening to the node location with electrically conductive material; rendering the sidewall spacer electrically conductive; and etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces.

Claim 30

A semiconductor processing method of forming a contact pedestal comprising the following steps: providing a conductive line having a node location adjacent thereto to which electrical connection is to be made; providing insulating dielectric material over the conductive line and the node location; etching a contact opening into the insulating dielectric material over the node location to a degree insufficient to outwardly expose the node location, the contact opening having a base positioned elevationally outward of the conductive line; providing a spacer layer over the insulating dielectric material to within the contact opening to a thickness which less than completely fills the contact opening; anisotropically etching the spacer layer to form a sidewall spacer within the contact opening and to outwardly expose the insulating dielectric material over the conductive line; after forming the sidewall spacer, etching through the contact opening base to outwardly expose the node location, the step of etching through the contact opening base also etching insulating dielectric material over the conductive line but to a degree insufficient to outwardly expose the conductive line; filling the contact opening to the node location with electrically conductive material; rendering the sidewall spacer electrically conductive; and etching the electrically conductive material to form an electrically conductive contact pedestal comprising the sidewall spacer, the pedestal having an outer surface which is substantially coplanar with opposing laterally adjacent electrically insulative surfaces.

Claim 31

The semiconductor processing method of forming a contact pedestal of claim 26 wherein the quantity of insulating material etched over the pair of wordlines during the step of etching through the contact opening base is greater than or equal to at least about 1.3 times the distance between the contact base and the node location.

Claim 32

The semiconductor processing method of forming a contact pedestal of claim 26 wherein the quantity of insulating material etched over the pair of wordlines during the step of etching through the contact opening base is equal to from about 1.3 to 1.5 times the distance between the contact base and the node location.

Claim 33

A semiconductor processing method of forming a plurality of contact pedestals comprising the following steps: providing a pair of field oxide regions and an active area therebetween relative to a semiconductor substrate; providing a pair of wordlines over the active area and first, second and third active area node locations adjacent thereto to which respective electrical connection is to be made; providing insulating dielectric material over the pair of wordlines and over the first node location, the second node location and the third node location; etching a first contact opening into the insulating dielectric material over the first node location, a second contact opening into the insulating dielectric material over the second node location and a third contact opening into the insulating dielectric material over the third node location; the first, second and third contact openings etching being conducted to a degree which is insufficient to outwardly expose any of the first, second and third node locations; the first contact opening having a first base, the second contact opening having a second base, the third contact opening having a third base; the first, second and third bases collectively being positioned elevationally outward of conductive portions of the pair of wordlines; providing a spacer layer over the insulating dielectric material to within the first, second and third contact openings to a thickness which less than completely fills each of the first, second and third contact openings; anisotropically etching the spacer layer to form a first sidewall spacer within the first contact opening, a second sidewall spacer within the second contact opening, and a third sidewall spacer within the third contact opening, and to outwardly expose insulating dielectric material over the pair of wordlines; after forming the sidewall spacers, etching through the first, second and third contact opening bases to outwardly expose the first, second, and third node locations; the step of collectively etching through the first, second and third contact opening bases also etching insulating dielectric material over the pair of wordlines but to a degree insufficient to outwardly expose the pair of wordlines; filling the first, second and third contact openings to the first, second and third node locations with electrically conductive material; rendering the first, second and third sidewall spacers electrically conductive; and etching the electrically conductive material inwardly to insulating dielectric material to form first, second and third electrically conductive contact pedestals; the first pedestal comprising the first sidewall spacer, the second pedestal comprising the second sidewall spacer, the third pedestal comprising the third sidewall spacer; the first, second and third pedestals having respective outer surfaces which are substantially coplanar with one another and a planar outer surface of the insulating dielectric material.

Claim 34

A semiconductor processing method of forming a plurality of contact pedestals comprising the following steps: providing a pair of field oxide regions and an active area therebetween relative to a semiconductor substrate; providing a pair of wordlines over the active area and first, second and third active area node locations adjacent thereto to which respective electrical connection is to be made; providing insulating dielectric material over the pair of wordlines and over the first node location, the second node location and the third node location; etching a first contact opening into the insulating dielectric material over the first node location, a second contact opening into the insulating dielectric material over the second node location and a third contact opening into the insulating dielectric material over the third node location; the first, second and third contact openings etching being conducted to a degree which is insufficient to outwardly expose any of the first, second and third node locations; the first contact opening having a first base, the second contact opening having a second base, the third contact opening having a third base; the first, second and third bases collectively being positioned elevationally outward of conductive portions of the pair of wordlines; providing a spacer layer over the insulating dielectric material to within the first, second and third contact openings to a thickness which less than completely fills each of the first, second and third contact openings; anisotropically etching the spacer layer to form a first sidewall spacer within the first contact opening, a second sidewall spacer within the second contact opening, and a third sidewall spacer within the third contact opening, and to outwardly expose insulating dielectric material over the pair of wordlines; after forming the sidewall spacers, etching through the first, second and third contact opening bases to outwardly expose the first, second, and third node locations; the step of collectively etching through the first, second and third contact opening bases also etching insulating dielectric material over the pair of wordlines but to a degree insufficient to outwardly expose the pair of wordlines; filling the first, second and third contact openings to the first, second and third node locations with electrically conductive material; rendering the first, second and third sidewall spacers electrically conductive; and etching the electrically conductive material inwardly to insulating dielectric material to form first, second and third electrically conductive contact pedestals; the first pedestal comprising the first sidewall spacer, the second pedestal comprising the second sidewall spacer, the third pedestal comprising the third sidewall spacer; the first, second and third pedestals having respective outer surfaces which are substantially coplanar with one another and a planar outer surface of the insulating dielectric material.

Claim 35

The semiconductor processing method of forming a plurality of contact pedestals of claim 29 wherein the spacer layer is provided to be electrically conductive prior to the anisotropic etching thereby rendering the first, second and third spacers to be electrically conductive immediately upon their formation.

Claim 36

The semiconductor processing method of forming a plurality of contact pedestals of claim 29 wherein the spacer layer is not provided to be electrically conductive prior to the anisotropic etching; the first, second, and third spacers being rendered electrically conductive after the anisotropic etching.

Claim 37

The semiconductor processing method of forming a plurality of contact pedestals of claim 29 wherein the insulating dielectric material includes an outermost surface, the outermost surface being substantially unplanarized prior to the etching step to form the pedestal.

Claim 38

The semiconductor processing method of forming a plurality of contact pedestals of claim 29 wherein the quantity of insulating material etched over the pair of wordlines during the step of etching through the contact opening base is greater than or equal to at least about 1.3 times the greatest distance between one of, i) the first contact base and the first node location, ii) the second contact base and the second node location, and iii) the third contact base and the third node location.

Claim 39

The semiconductor processing method of forming a plurality of contact pedestals of claim 29 wherein the quantity of insulating material etched over the pair of wordlines during the step of etching through the contact opening base is equal to from about 1.3 to 1.5 times the greatest distance between one of, i) the first contact base and the first node location, ii) the second contact base and the second node location, and iii) the third contact base and the third node location.