EP0540930A2
Expired / Lapsed
EP
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Bit line configuration for semiconductor memory
Assignee: International Business Machines Corp
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Filing: 1992-10-19
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Granted: —
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Expires: 2012-10-19
Abstract
Abstract A new interdigitated folded bit line (IFBL) architecture for a future generation high density semiconductor memory design is disclosed. In the architecture, the basic cross-point memory cells are organized orthogonally in rows and columns to form an array matrix. The bit lines run in a row direction while the word lines run in a column direction. Transfer transistors are designed to be shared with the same drain junction and the same bit line contact in order to save area. A choice of at least two described embodiments are provided. In one embodiment, referred to as the offset bit line structure, the bit lines are constructed by using two layers of interconnection lines to connect the interdigitated cells associated to it. By connecting the bit line contacts with two different interconnecting layers in an alternating row order, the true and complement bit lines will run parallel to both sides of the memory array. In another embodiment, referred to as the side wall bit line structure, the bit lines are constructed by using the conductive side wall spacer rails to connect the interdigitated cells associated to it. By connecting the side wall bit line contacts with two sided-side wall spacer rails in an alternating row order, the true and complement bit lines will run parallel to both sides of the memory array.
Inventors
- 👤 Sang Hoo Dhong
- 👤 Wei Hwang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 03:48
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; Y; Y10; Y10S; Y10S257/00; Y10S257/907
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
241 words
A folded bit line configuration for a semiconductor memory device comprising: a substrate (80) having a plurality of spaced drain junction regions (96) in the surface thereof, a first insulating layer (90) disposed over said substrate, a first plurality of conductive bit line pairs (32) disposed on said first insulating layer, each including a first and a second conductive bit line extending in a first direction on said first insulating layer, a second insulating layer disposed over said first insulating layer (92), and said first plurality of conductive bit line pairs, a second plurality of conductive bit line pairs (30) disposed on said second insulating layer, each including a first and a second conductive bit line extending in said first direction on said second insulating layer wherein said bit lines on said second insulating layer are disposed above and laterally offset relative to said bit lines on said first insulating layer, a first plurality of electrically conductive contact means (58, 68) disposed in said first insulating layer and each extending from a first selected drain junction region to a first bit line of said first plurality of bit line pairs on said first insulating layer, a second plurality of electrically conductive contact means (59, 69) disposed in said first and second insulating layers and each extending from a second selected drain junction region to a second bit line of said second plurality of bit line pairs on said second insulating layer.
Claim 2
Dependent Claim
109 words
A folded bit line configuration for a semiconductor memory device according to Claim 1 further including a first plurality of sense amplifiers (22), each sense amplifier of said first plurality having an input connected to a separate bit line pair disposed on said first insulating layer or pair of side wall spacer bit lines disposed on said first side of said pillars, respectively, and a second plurality of sense amplifiers, each sense amplifier of said second plurality having an input connected to a separate bit line pair disposed on said second insulating layer or pair of side walls spacer bit lines disposed on said second side of said pillars.
Claim 3
Dependent Claim
84 words
A folded bit line configuration for a semiconductor memory device according to Claim 2 wherein said first plurality of sense amplifiers are located in said semiconductor memory device at one end of said bit line pairs and said second plurality of sense amplifiers are located in said semiconductor memory device at the other end of said bit line pairs such that said bit line pairs extend between said first plurality of sense amplifiers and said second plurality of sense amplifiers in said memory device.
Claim 4
Dependent Claim
77 words
A folded bit line configuration for a semiconductor memory device according to Claim 3 further including a plurality of conductive word lines pairs (42) disposed on said substrate between said first and second plurality of sense amplifiers and extending in parallel in a direction orthogonal to said first direction of said bit line pairs, each of said word line pairs including first and second word lines extending on either side of said first and second contact means.
Claim 5
Dependent Claim
118 words
A folded bit line configuration for a semiconductor memory device according to Claim 4 wherein said first and second plurality of bit line pairs extending in said first direction on said first and second insulating layers and said word lines extending in said second direction on said substrate form a multi-layer configuration of bit line and word line crossover positions wherein said first and second contact means are disposed in alternate positions at the crossover positions of said first bit lines of said first and second plurality of bit line pairs with said word lines and the crossover positions of said second bit lines of said first and second plurality of bit line pairs with said word lines.
Claim 6
Dependent Claim
76 words
A folded bit line configuration for a semiconductor memory device according to Claim 3 further including a plurality of word line pairs each including first and second word lines disposed on said substrate on either side of said bit line studs in parallel in a direction orthogonal to said first direction of said bit lines, said bit line pairs and said word line pairs form a multi-layer configuration of bit line and word line crossover positions.
Claim 7
Dependent Claim
46 words
A folded bit line configuration for a semiconductor memory device according to Claim 5 or 6 further including a memory cell located at each of said crossover positions, and wherein adjacent ones of said memory cells share a common drain junction and bit line contact means.
Claim 8
Dependent Claim
203 words
A folded bit line configuration for a semiconductor memory device according to Claim 1 wherein each of said first plurality of conductive contact means includes a first bit line stud (54) disposed on said substrate (80) in contact with a first selected drain junction region (96), a first metal contact element (58) disposed directly over and in contact with said first drain junction, and a first bit line connection element (59) disposed directly between said first metal contact element and a first bit line of said first plurality of conductive bit line pairs on said first insulating layer, and wherein each of said second plurality of conductive contact means includes a second bit line stud (64) disposed on said substrate in contact with a second selected drain junction spaced proximate to said first selected drain junction, a second metal contact element (68) disposed over and in contact with said second bit line stud, said second metal contact element being offset relative to said second bit line stud therebeneath, and a second bit line connection element disposed (67) directly between said second metal contact element and a second bit line of said second plurality of conductive bit line pairs on said second insulating layer.
Claim 9
Dependent Claim
167 words
A folded bit line configuration for a semiconductor memory device comprising a substrate (80) having a plurality of spaced drain regions in the surface thereof, a conductive bit line stud (57) disposed over and in contact with each of said plurality of drain regions, a pillar (102) of conductive material disposed on each of said conductive material disposed on each of said conductive bit line studs, each of said pillars having a first vertical side and a second vertical side opposite to said first vertical side, a layer of insulating material disposed on said first vertical side of every alternative ones of said plurality of pillars, a layer of insulating material disposed on said second vertical side of the other of said alternative ones of said plurality of pillars not having insulating material on said first side, conductive side wall spacer bit line rails (100, 110) disposed on both said first and second sides of said plurality of pillars and extending in parallel in a first direction.
Claim 10
Independent Claim
237 words
A method for fabricating a folded bit line structure for a semiconductor memory device comprising the steps of: 1) providing a substrate containing a plurality of spaced drain junction regions therein, 2) forming a plurality of first and second conductive contact means alternatively connected above separate ones of said plurality of drain junction regions, 3) planarizing said contact means with a first layer of insulating material, 4) forming a first plurality of conductive bit line pairs on said first layer of insulating material, said bit line pairs each containing a first and a second bit line wherein said first bit lines of said first plurality of bit line pairs are formed over and in contact with separate ones of said first conductive contact means, 5) forming a second layer of insulating material over said first plurality of bit line pairs and said first insulating layer, 6) forming a plurality of third conductive contact means in said second insulating layer, each connected to a separate one of said second conductive contacts in said first insulating layer, 7) forming a second plurality of conductive bit line pairs on said second layer of insulating material said second plurality of bit line pairs each containing a first and a second bit line wherein said second bit lines of said second plurality of bit line pairs are formed over and in contact with a separate one of said third conductive contact means.
Claim 11
Independent Claim
167 words
A method of fabricating a folded bit line structure for a semiconductor memory device comprising the steps of: 1) providing a substrate containing a plurality of spaced drain junction regions therein, 2) forming a conductive bit line stud over each of said plurality of drain regions, 3) forming a vertical pillar over each of said plurality of conductive bit line studs, 4) depositing a layer of insulating material on the top and sides of each of said plurality of pillars, 5) removing said insulating material from a first side of alternating ones of said plurality of pillars, 6) removing said insulating material from a second side opposite to said first side of the other of said plurality of pillars disposed between said pillars having said insulating material removed from said first side, 7) forming conductive pairs of conductive spacer rail bit line pairs, one bit line spacer rail of each pair being disposed on said first and second opposite side of each of said plurality of pillars.
References Cited (Backward Citations)
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