US5330934A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a semiconductor device having miniaturized contact electrode and wiring structure
Assignee: Toshiba Corp
•
Filing: 1993-06-16
•
Granted: 1994-07-19
•
Expires: 2013-06-16
Abstract
Abstract A contact hole in a diffusion region is narrowed by a buffer layer formed at about the middle of an interlayer insulating film in its thickness direction. This buffer layer serves as effective alignment tolerances to the diffusion region and a contact electrode at the time of forming the contact hole. The structure having a wiring conductor filled in the contact hole and having the contact electrode formed on this wiring conductor can assure a highly reliable contact. Forming a buffer layer as a sidewall on this contact electrode and a first wiring layer formed on the same layer can assure an effective alignment tolerance to the first wiring layer at the time of forming a via hole. Filling a wiring conductor in the via hole can eliminate the need for any contact tolerance for a second wiring layer to be formed on this wiring conductor. Accordingly, the individual contact tolerances can be assured by self-alignment.
Inventors
- 👤 Hideki Shibata
- 👤 Naoki Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 03:01
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/425; H10W72/00; H10W72/01; H10W72/019; H10W72/90; H10W72/951; H10W72/952
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
212 words
A method of fabricating a semiconductor having a miniaturized contact electrode and wiring structure, comprising the steps of: forming an interlayer insulating film on a semiconductor substrate; forming a first buffer layer on said interlayer insulating film and a stopper insulating film on said first buffer layer; selectively forming in said interlayer insulating film a first opening having a bottom inside said interlayer insulating film and shallower than a thickness of said interlayer insulating film; forming a second buffer layer to cover said first opening and said stopper insulating film; performing anisotropic etching to leave said second buffer layer on a sidewall of said first opening; executing anisotropic etching with said first and second buffer layers used as masks to penetrate that part of said bottom of said first opening which is exposed, and forming a second opening to expose a surface of said semiconductor substrate; filling a wiring conductor in said second opening and said first opening following said second opening; forming a contact electrode on said wiring conductor filled in said first opening as wide as a width of said first opening; and depositing a third buffer layer to cover said contact electrode, and performing anisotropic etching to leave said third buffer layer on a sidewall of said contact electrode.
Claim 2
Independent Claim
212 words
A method of fabricating a semiconductor having a miniaturized contact electrode and wiring structure, comprising the steps of: forming an interlayer insulating film on a semiconductor substrate; forming a first buffer layer on said interlayer insulating film and a stopper insulating film on said first buffer layer; selectively forming in said interlayer insulating film a first opening having a bottom inside said interlayer insulating film and shallower than a thickness of said interlayer insulating film; forming a second buffer layer to cover said first opening and said stopper insulating film; performing anisotropic etching to leave said second buffer layer on a sidewall of said first opening; executing anisotropic etching with said first and second buffer layers used as masks to penetrate that part of said bottom of said first opening which is exposed, and forming a second opening to expose a surface of said semiconductor substrate; filling a wiring conductor in said second opening and said first opening following said second opening; forming a contact electrode on said wiring conductor filled in said first opening as wide as a width of said first opening; and depositing a third buffer layer to cover said contact electrode, and performing anisotropic etching to leave said third buffer layer on a sidewall of said contact electrode.
Claim 3
Dependent Claim
22 words
A method according to claim 1, wherein said first, second and third buffer layers are conductive films formed by a CVD method.
Claim 4
Dependent Claim
26 words
A method according to claim 2, wherein said first, second and third buffer layers are films essentially consisting of silicon and formed by a CVD method.
Claim 5
Dependent Claim
39 words
A method according to claim 3, wherein said third buffer layer is formed using a SiH 4 /Ar gas system by a plasma CVD method at a lower temperature than when said first and second buffer layers are formed.
Claim 6
Dependent Claim
44 words
A method according to claim 1, wherein that surface of said semiconductor substrate which is to be electrically connected via said first and second openings to said contact electrode has undergone a step of implanting a conductive impurity, and is a conductive impurity region.
Claim 7
Dependent Claim
19 words
A method according to claim 1, wherein said wiring conductor contains silicon and is formed by a CVD method.
Claim 8
Dependent Claim
22 words
A method according to claim 1, wherein said wiring conductor includes a high-melting point metal and is formed by a CVD method.
Claim 9
Dependent Claim
21 words
A method according to claim 7, wherein said high-melting point metal is tungsten and is formed by a a CVD method.
Claim 10
Dependent Claim
48 words
A method according to claim 1, wherein said interlayer insulating film comprises at least two types of layers having different etching rates, and in executing etching by an RIE method in said step of selectively forming said first opening, said etching is stopped where said etching rate changes.
Claim 11
Independent Claim
290 words
A method of fabricating a semiconductor having a miniaturized contact electrode and wiring structure, comprising the steps of: forming a first interlayer insulating film on a semiconductor substrate; forming a first buffer layer on said first interlayer insulating film and a stopper insulating film on said first buffer layer; selectively forming a first opening having a bottom inside said first interlayer insulating film and shallower than a thickness of said first interlayer insulating film; forming a second buffer layer to cover said first opening and said stopper insulating film; performing anisotropic etching to leave said second buffer layer on a sidewall of said first opening; executing anisotropic etching with said first and second buffer layers used as masks to penetrate that part of said bottom of said first opening which is exposed, and forming a second opening to expose a face of said semiconductor substrate; filling a first wiring conductor in said second opening and said first opening following said second opening; forming a contact electrode on said first wiring conductor filled in said first opening as wide as a width of said first opening, and selectively forming a first wiring layer on said first interlayer insulating film; depositing a third buffer layer and performing anisotropic etching to leave said third buffer layer on sidewalls of said contact electrode and said first wiring layer; forming a second interlayer insulating film to cover said contact electrode and said first wiring layer, and forming a third opening in said second interlayer insulating film so as to expose said first wiring layer; forming a second wiring conductor on said first wiring layer so as to fill an interior of said third opening; and forming a second wiring layer on said second wiring conductor.
Claim 12
Independent Claim
290 words
A method of fabricating a semiconductor having a miniaturized contact electrode and wiring structure, comprising the steps of: forming a first interlayer insulating film on a semiconductor substrate; forming a first buffer layer on said first interlayer insulating film and a stopper insulating film on said first buffer layer; selectively forming a first opening having a bottom inside said first interlayer insulating film and shallower than a thickness of said first interlayer insulating film; forming a second buffer layer to cover said first opening and said stopper insulating film; performing anisotropic etching to leave said second buffer layer on a sidewall of said first opening; executing anisotropic etching with said first and second buffer layers used as masks to penetrate that part of said bottom of said first opening which is exposed, and forming a second opening to expose a face of said semiconductor substrate; filling a first wiring conductor in said second opening and said first opening following said second opening; forming a contact electrode on said first wiring conductor filled in said first opening as wide as a width of said first opening, and selectively forming a first wiring layer on said first interlayer insulating film; depositing a third buffer layer and performing anisotropic etching to leave said third buffer layer on sidewalls of said contact electrode and said first wiring layer; forming a second interlayer insulating film to cover said contact electrode and said first wiring layer, and forming a third opening in said second interlayer insulating film so as to expose said first wiring layer; forming a second wiring conductor on said first wiring layer so as to fill an interior of said third opening; and forming a second wiring layer on said second wiring conductor.
Claim 13
Dependent Claim
22 words
A method according to claim 10, wherein said first, second and third buffer layers are conductive films formed by a CVD method.
Claim 14
Dependent Claim
26 words
A method according to claim 10, wherein said first, second and third buffer layers are films essentially consisting of silicon and formed by a CVD method.
Claim 15
Dependent Claim
39 words
A method according to claim 12, wherein said third buffer layer is formed using a SiH 4 /Ar gas system by a plasma CVD method at a lower temperature than when said first and second buffer layers are formed.
Claim 16
Dependent Claim
44 words
A method according to claim 10, wherein that surface of said semiconductor substrate which is to be electrically connected via said first and second openings to said contact electrode has undergone a step of implanting a conductive impurity, and is a conductive impurity region.
Claim 17
Dependent Claim
19 words
A method according to claim 10, wherein said wiring conductor contains silicon and is formed by a CVD method.
Claim 18
Dependent Claim
22 words
A method according to claim 10, wherein said wiring conductor includes a high-melting point metal and is formed by a CVD method.
Claim 19
Dependent Claim
20 words
A method according to claim 16, wherein said high-melting point metal is tungsten and is formed by a CVD method.
Claim 20
Dependent Claim
48 words
A method according to claim 10, wherein said interlayer insulating film comprises at least two types of layers having different etching rates, and in executing etching by an RIE method in said step of selectively forming said first opening, said etching is stopped where said etching rate changes.
Claim 21
Dependent Claim
69 words
A method according to claim 10, wherein in said step of forming said contact electrode on said first wiring conductor filled in said first opening as wide as said width of said first opening and selectively forming said first wiring layer on said first interlayer insulating film, said first buffer layer is left on said first interlayer insulating film and said first wiring layer on said first buffer layer.
References Cited (Backward Citations)
US4619037A
Cited
JPS59200439A
Cited
US4641170A
Cited
US4874719A
Cited
JPS6373537A
Cited
US4866009A
Cited
US4878105A
Cited
JPS6457645A
Cited
US4962414A
Cited
US5204286A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-18 | 1998-01-17 | 1998-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-18 | 2002-01-17 | 2002-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-18 | 2006-01-17 | 2006-07-19 | $7700.00 | Window Closed / Lapsed |