Non-random sub-lithography vertical stack capacitor

Abstract

Abstract Integrated circuit structures of sub-lithography dimensions are formed by conformal deposition of alternating layers of materials having differing etch rates within an aperture over a body of material to be etched. One of the materials in the alternating layers is then selectively and preferentially etched to form a mask through which etching can be performed on the body of material to be etched. Large polysilicon blocks or plugs (38) are formed onto a conventional interconnect structure for accessing a memory cell prior to forming a capacitor which can extend over a portion of a bit line and the insulating cap and sidewalls. This is preferably done by providing a thick polysilicon deposition in a blanket layer by any known process. This blanket layer is then preferably planarized and then etched to separate the layer into blocks or plugs which are in contact with the conductive studs connected to transistors. Deep grooves are formed in the polysilicon plug (38). The polysilicon plug is surrounded with TEOS oxide and includes concentric rings which are of sustantial mechanical integrity, particularly after a oxide-nitride-oxide (ONO) layer (60) of about 5 nm thickness is conformally deposited in the grooves and the remainder of the grooves are filled with a conductor (62) such as aluminium or polysilicon to complete the other capacitor plate. This technique is particularly suited to the formation of structurally robust capacitors for memory cells which have greatly increased plate area, resulting in increased capacitance, while maintaining a small footprint for the capacitor structure.

Inventors

• 👤 Bomy Able Chen
• 👤 Son Van Nguyen
• 👤 Gary Bela Bronner

Bibliographic Details