Method for manufacturing crown-shaped storage capacitors on dynamic random access memory cells

Claim 1

A method for fabricating an array of crown-shaped capacitors on a semiconductor substrate in device areas, comprising the steps of: providing a semiconductor substrate having field oxide areas surrounding and electrically isolating an array of device areas, each of said device areas having a single field effect transistor (FET) consisting of a gate electrode and having a first and second source/drain areas adjacent to and on each side of said gate electrode, and forming bit line contacts and interconnecting electrically conducting bit lines to said first source/drain areas, and further forming the crown-shape node capacitors by; depositing a low flow temperature insulator on said field effect transistors and elsewhere on said substrate, annealing said low flow temperature insulator and forming an essentially planar surface on said low flow temperature insulator, forming contact openings in said low flow temperature insulator to said second source/drain area of each of said field effect transistors, depositing a conformal bottom electrode polysilicon layer in said node contact openings and elsewhere on said substrate, and thereby filling said contact openings and making electrical contact to said second source/drain areas, and forming an essentially planar bottom electrode polysilicon layer on said substrate; spin coating a positive photoresist layer on said planar bottom electrode polysilicon layer; optically exposing said positive photoresist layer using a phase-shift edge mask having an array of 180 degree phase shifting material regions aligned over the planned capacitor areas, developing said photoresist, and thereby forming a crown-shaped patterned photoresist mask on said capacitor areas; and replicating said pattern photoresist mask in said bottom electrode polysilicon layer by anisotropic etching; removing said patterned photoresist layer, and thereby forming an array of crown-shaped bottom electrodes for said array of crown-shaped stacked capacitors; forming an interelectrode dielectric layer on surfaces of said crown-shaped bottom electrodes, depositing a top electrode polysilicon layer on said dielectric layer and elsewhere on said substrate; patterning said top electrode polysilicon layer and thereby forming the top electrodes of said storage capacitors and completing said array of crown-shaped stacked capacitors.

Claim 2

A method for fabricating an array of crown-shaped capacitors on a semiconductor substrate in device areas, comprising the steps of: providing a semiconductor substrate having field oxide areas surrounding and electrically isolating an array of device areas, each of said device areas having a single field effect transistor (FET) consisting of a gate electrode and having a first and second source/drain areas adjacent to and on each side of said gate electrode, and forming bit line contacts and interconnecting electrically conducting bit lines to said first source/drain areas, and further forming the crown-shape node capacitors by; depositing a low flow temperature insulator on said field effect transistors and elsewhere on said substrate, annealing said low flow temperature insulator and forming an essentially planar surface on said low flow temperature insulator, forming contact openings in said low flow temperature insulator to said second source/drain area of each of said field effect transistors, depositing a conformal bottom electrode polysilicon layer in said node contact openings and elsewhere on said substrate, and thereby filling said contact openings and making electrical contact to said second source/drain areas, and forming an essentially planar bottom electrode polysilicon layer on said substrate; spin coating a positive photoresist layer on said planar bottom electrode polysilicon layer; optically exposing said positive photoresist layer using a phase-shift edge mask having an array of 180 degree phase shifting material regions aligned over the planned capacitor areas, developing said photoresist, and thereby forming a crown-shaped patterned photoresist mask on said capacitor areas; and replicating said pattern photoresist mask in said bottom electrode polysilicon layer by anisotropic etching; removing said patterned photoresist layer, and thereby forming an array of crown-shaped bottom electrodes for said array of crown-shaped stacked capacitors; forming an interelectrode dielectric layer on surfaces of said crown-shaped bottom electrodes, depositing a top electrode polysilicon layer on said dielectric layer and elsewhere on said substrate; patterning said top electrode polysilicon layer and thereby forming the top electrodes of said storage capacitors and completing said array of crown-shaped stacked capacitors.

Claim 11

A method for manufacturing an array of dynamic random access memory cells having crown-shaped stacked capacitors on a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having field oxide areas surrounding and electrically isolating an array of device areas, each of said device areas having a single field effect transistor (FET) consisting of a gate oxide, a gate electrode formed from a patterned first polysilicon layer and a silicide layer, and having a cap oxide thereon, each of said FETs having a first and second source/drain areas adjacent to and on each side of said gate electrode, and insulating sidewalls, said patterned first polysilicon layer and silicide layer also forming interconnecting word lines for said field effect transistors; depositing a first insulating layer on said field effect transistors and elsewhere on said substrate; masking and etching contact openings in said first insulating layer to said first source/drain area of each field effect transistor, and thereby forming bit line contact openings; depositing a second polysilicon layer over said first insulating layer and in said bit line contact openings; patterning by masking and etching said second polysilicon layer, and thereby forming interconnecting bit lines to said bit line contact openings; depositing a second insulating layer over said bit lines and elsewhere on said substrate; depositing a third insulating layer composed of a low flow temperature glass, and annealing said glass, and thereby forming an essentially planar surface on said third insulating layer; depositing a third polysilicon layer on said third insulating layer; masking and etching node contact openings in said third polysilicon layer and partially into said third insulating layer, said node contact openings aligned over said second source/drain areas of each of said field effect transistors; depositing a conformal fourth polysilicon layer; anisotropically etching back said fourth polysilicon layer to said third insulating layer in said node contact openings, and thereby forming sidewall spacer and reducing the width of said node contact openings; anisotropically and selectively etching said third insulating layer in said node contact openings to the surface of said second source/drain areas, said third and fourth polysilicon layers serving as an etch mask; depositing a conformal fifth polysilicon layer in said node contact openings and elsewhere on said third polysilicon layer, and having an essentially planar surface; spin coating a positive photoresist layer on said fifth polysilicon layer; optically exposing said positive photoresist layer using a phase-shift edge mask having an array of 180 degree phase shifting material regions aligned over the planned capacitor areas, and developing said photoresist, and thereby forming a crown-shaped photoresist mask on said capacitor areas; and patterning said fifth polysilicon layer by anisotropic etching; removing said patterned photoresist layer, and thereby forming an array of crown-shaped bottom electrodes for said array of crown-shaped stacked capacitors; forming an interelectrode dielectric layer on surfaces of said crown-shaped bottom electrodes, depositing a sixth polysilicon layer on said dielectric layer and elsewhere on said third insulating layer; patterning said sixth polysilicon layer and forming the top electrodes of said storage capacitors and thereby completing said array of DRAM memory cells having crown-shaped stacked capacitors.

Claim 12

A method for manufacturing an array of dynamic random access memory cells having crown-shaped stacked capacitors on a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having field oxide areas surrounding and electrically isolating an array of device areas, each of said device areas having a single field effect transistor (FET) consisting of a gate oxide, a gate electrode formed from a patterned first polysilicon layer and a silicide layer, and having a cap oxide thereon, each of said FETs having a first and second source/drain areas adjacent to and on each side of said gate electrode, and insulating sidewalls, said patterned first polysilicon layer and silicide layer also forming interconnecting word lines for said field effect transistors; depositing a first insulating layer on said field effect transistors and elsewhere on said substrate; masking and etching contact openings in said first insulating layer to said first source/drain area of each field effect transistor, and thereby forming bit line contact openings; depositing a second polysilicon layer over said first insulating layer and in said bit line contact openings; patterning by masking and etching said second polysilicon layer, and thereby forming interconnecting bit lines to said bit line contact openings; depositing a second insulating layer over said bit lines and elsewhere on said substrate; depositing a third insulating layer composed of a low flow temperature glass, and annealing said glass, and thereby forming an essentially planar surface on said third insulating layer; depositing a third polysilicon layer on said third insulating layer; masking and etching node contact openings in said third polysilicon layer and partially into said third insulating layer, said node contact openings aligned over said second source/drain areas of each of said field effect transistors; depositing a conformal fourth polysilicon layer; anisotropically etching back said fourth polysilicon layer to said third insulating layer in said node contact openings, and thereby forming sidewall spacer and reducing the width of said node contact openings; anisotropically and selectively etching said third insulating layer in said node contact openings to the surface of said second source/drain areas, said third and fourth polysilicon layers serving as an etch mask; depositing a conformal fifth polysilicon layer in said node contact openings and elsewhere on said third polysilicon layer, and having an essentially planar surface; spin coating a positive photoresist layer on said fifth polysilicon layer; optically exposing said positive photoresist layer using a phase-shift edge mask having an array of 180 degree phase shifting material regions aligned over the planned capacitor areas, and developing said photoresist, and thereby forming a crown-shaped photoresist mask on said capacitor areas; and patterning said fifth polysilicon layer by anisotropic etching; removing said patterned photoresist layer, and thereby forming an array of crown-shaped bottom electrodes for said array of crown-shaped stacked capacitors; forming an interelectrode dielectric layer on surfaces of said crown-shaped bottom electrodes, depositing a sixth polysilicon layer on said dielectric layer and elsewhere on said third insulating layer; patterning said sixth polysilicon layer and forming the top electrodes of said storage capacitors and thereby completing said array of DRAM memory cells having crown-shaped stacked capacitors.