US6049223A — Programmable logic array integrated circuit with …

Claim 1

Independent Claim 148 words

A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, and a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; and a pad coupled to provide addresses to an address bus of said memory block from an external source to said programmable logic device integrated circuit.

Claim 2

Dependent Claim 148 words

A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, and a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; and a pad coupled to provide addresses to an address bus of said memory block from an external source to said programmable logic device integrated circuit.

Claim 3

Dependent Claim 24 words

The programmable logic device integrated circuit of claim 1 wherein a word size and a depth size for said memory block are programmably selectable.

Claim 4

Dependent Claim 83 words

The programmable logic device integrated circuit of claim 1 wherein said memory organization of said memory block is configurable in a third mode, wherein said memory block has a first number of bits width and a second number of bits depth, and said memory block is configurable in a fourth mode, wherein said memory block has a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

Claim 5

Dependent Claim 17 words

The programmable logic device integrated circuit of claim 1 wherein said memory block is a dual-port memory.

Claim 6

Dependent Claim 17 words

The programmable logic device integrated circuit of claim 1 wherein said memory block is a single-port memory.

Claim 7

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 1 wherein said first plurality of conductors is coupled to an address bus of said memory block.

Claim 8

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 1 wherein said first plurality of conductors is coupled to a data bus of said memory block.

Claim 9

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 1 wherein an output bus of said memory block is coupled to said first plurality of conductors.

Claim 10

Dependent Claim 19 words

The programmable logic device integrated circuit of claim 1 wherein said user-programmable memory bit is a floating gate device.

Claim 11

Dependent Claim 18 words

The programmable logic device integrated circuit of claim 1 wherein said user-programmable memory bit is an antifuse element.

Claim 12

Dependent Claim 18 words

The programmable logic device integrated circuit of claim 1 wherein said user-programmable memory bit is an SRAM cell.

Claim 13

Dependent Claim 31 words

The programmable logic device integrated circuit of claim 1 further comprising: a global clock signal, coupled to at least one of said plurality of logic array blocks and said memory block.

Claim 14

Dependent Claim 19 words

The programmable logic device integrated circuit of claim 1 wherein said programmable logic device is configurable by in-system programming.

Claim 15

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 1 wherein said memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs controls operations of said memory block.

Claim 16

Dependent Claim 44 words

The programmable logic device integrated circuit of claim 1 wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, a plurality of control inputs for said memory block.

Claim 17

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 1 wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block.

Claim 18

Dependent Claim 30 words

The programmable logic device integrated circuit of claim 1 wherein at least one logic element is coupled directly to said memory block without passing through said second plurality of conductors.

Claim 19

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 1 wherein said second plurality of conductors is programmably coupled to said memory block using fully populated multiplexing.

Claim 20

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 1 wherein said second plurality of conductors is programmably coupled to said memory block using partially populated multiplexing.

Claim 21

Dependent Claim 42 words

The programmable logic device integrated circuit of claim 1 further comprising: a crossbar switch, coupled between said memory block and said second plurality of conductors, wherein said second plurality of conductors is programmably coupled to said crossbar switch using partially populated multiplexing.

Claim 22

Dependent Claim 45 words

The programmable logic device integrated circuit of claim 1 further comprising: a plurality of input-output blocks, coupled to said plurality of logic array blocks; and an output enable signal, programmably coupled to at least one of said plurality of input-output blocks and said memory block.

Claim 23

Dependent Claim 35 words

A digital processing system comprising: a processing unit; a memory, coupled to said processing unit; and a programmable logic device integrated circuit as recited in claim 1, coupled to said processing unit and said memory.

Claim 24

Dependent Claim 59 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said logic elements; and a first-in, first-out memory block, programmably coupled to said programmable interconnect array, wherein a memory organization of said first-in, first-out memory block is programmably configurable via a user-programmable memory bit.

Claim 25

Dependent Claim 59 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said logic elements; and a first-in, first-out memory block, programmably coupled to said programmable interconnect array, wherein a memory organization of said first-in, first-out memory block is programmably configurable via a user-programmable memory bit.

Claim 26

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 23 wherein a width of said first-in, first-out memory block is variable by configuring said user-programmable memory bit.

Claim 27

Dependent Claim 25 words

The programmable logic integrated circuit of claim 23 wherein a word size and a depth size for said first-in, first-out memory block are programmably selectable.

Claim 28

Dependent Claim 74 words

The programmable logic integrated circuit of claim 23 wherein said memory organization of said first-in, first-out memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and configurable in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

Claim 29

Dependent Claim 50 words

The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block comprises a plurality of flags indicating status information of said first-in, first-out memory block, wherein said plurality of flags may be programmably coupled through said programmable interconnect array to drive logic of said programmable logic device.

Claim 30

Dependent Claim 36 words

The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block comprises an ENABLE WRITE control input, coupled from said logic elements, to control writing of data into said first-in, first-out memory module.

Claim 31

Dependent Claim 36 words

The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block comprises an ENABLE READ control input, coupled from said logic elements, to control reading of data from said first-in, first-out memory module.

Claim 32

Dependent Claim 35 words

The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block comprises a CLEAR control input, coupled from said logic elements, to control resetting control logic within said first-in, first-out memory module.

Claim 33

Dependent Claim 47 words

The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block generates an ALMOST FULL flag, user-programmable to indicate a number of unoccupied memory locations in said first-in, first-out memory, wherein said ALMOST FULL flag may be programmably coupled to said programmable interconnect array.

Claim 34

Dependent Claim 26 words

The programmable logic integrated circuit of claim 31 wherein said ALMOST FULL flag is FALSE when said number of unoccupied memory locations exceeds a user-selected value.

Claim 35

Dependent Claim 47 words

The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block generates an ALMOST EMPTY flag, user-programmable to indicate a number of occupied memory locations in said first-in, first-out memory, wherein said ALMOST EMPTY flag may be programmably coupled to said programmable interconnect array.

Claim 36

Dependent Claim 26 words

The programmable logic integrated circuit of claim 23 wherein said ALMOST EMPTY flag is FALSE when said number of occupied memory locations exceeds a user-selected value.

Claim 37

Dependent Claim 29 words

The programmable logic integrated circuit of claims 32 or 34 wherein said user-selected value is stored in said programmable logic device using electrically erasable programmable read only memory cells.

Claim 38

Dependent Claim 105 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and a memory block programmably coupled to said programmable interconnect array, said memory block programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, said memory block comprising: a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and an address bus accessible from a second pad.

Claim 39

Dependent Claim 105 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and a memory block programmably coupled to said programmable interconnect array, said memory block programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, said memory block comprising: a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and an address bus accessible from a second pad.

Claim 40

Dependent Claim 26 words

The programmable logic integrated circuit of claim 36 wherein accessibility to said data bus from said programmable interconnect array or said first pad is programmably configurable.

Claim 41

Dependent Claim 26 words

The programmable logic integrated circuit of claim 36 wherein concurrent access to said memory block from said programmable interconnect array and said first pad is permitted.

Claim 42

Dependent Claim 19 words

The programmable logic integrated circuit of claim 36 wherein said address bus is accessible from said programmable interconnect array.

Claim 43

Dependent Claim 32 words

The programmable logic integrated circuit of claim 36 wherein said memory block further comprises: an output bus, programmably configurable to provide data output to said programmable interconnect array or a third pad.

Claim 44

Dependent Claim 23 words

The programmable logic integrated circuit of claim 40 wherein said output bus is programmably coupled to provide data output to said data bus.

Claim 45

Dependent Claim 14 words

The programmable logic integrated circuit of claim 36 wherein said memory block is dual-ported.

Claim 46

Dependent Claim 14 words

The programmable logic integrated circuit of claim 36 wherein said memory block is single-ported.

Claim 47

Dependent Claim 40 words

The programmable logic integrated circuit of claim 36 wherein said memory block further comprises: a plurality of control inputs to control operation of said memory block, wherein said plurality of control inputs is programmably coupled to the programmable interconnect array.

Claim 48

Dependent Claim 34 words

The programmable logic integrated circuit of claim 36 wherein said memory block further comprises: a busy flag signal to indicate whether a read port and a write port are addressing a similar memory location.

Claim 49

Dependent Claim 37 words

The programmable logic integrated circuit of claim 36 wherein said memory block further comprises: a first portion of memory cells; and a second portion of memory cells, wherein said first and second portions are coupled in parallel.

Claim 50

Dependent Claim 26 words

The programmable logic integrated circuit of claim 36 wherein a memory organization of said memory block is programmably configurable via at least one user-programmable memory cell.

Claim 51

Dependent Claim 73 words

The programmable logic device integrated circuit of claim 47 wherein said memory organization of said memory block is configurable in a third mode to have a first number of bits width and a second number of bits depth, and configurable in a fourth mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

Claim 52

Dependent Claim 114 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and a memory module, programmably coupled to said programmable interconnect array, wherein said memory module programmably is configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, and said memory module comprises: a read address bus accessible from said programmable interconnect array or a first pad, said first pad coupled to provide data external to said programmable logic integrated circuit, whereby said read address bus provides memory addresses for reading data from said memory module.

Claim 53

Dependent Claim 114 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and a memory module, programmably coupled to said programmable interconnect array, wherein said memory module programmably is configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, and said memory module comprises: a read address bus accessible from said programmable interconnect array or a first pad, said first pad coupled to provide data external to said programmable logic integrated circuit, whereby said read address bus provides memory addresses for reading data from said memory module.

Claim 54

Dependent Claim 43 words

The programmable logic integrated circuit of claim 49 wherein said memory module further comprises: a write address bus accessible from said programmable interconnect array or said first pad, whereby said write address bus provides memory addresses for writing data to said memory block.

Claim 55

Dependent Claim 27 words

The programmable logic integrated circuit of claim 49 wherein said memory module further comprises: a data bus accessible from said programmable interconnect array or said first pad.

Claim 56

Dependent Claim 128 words

A programmable logic integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is a dual-port memory, and a memory organization of said memory block is programmably selectable a user-programmable memory bit; and a pad coupled to provide addresses to an address bus of said memory block from an external source to said programmable logic device integrated circuit.

Claim 57

Dependent Claim 128 words

A programmable logic integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is a dual-port memory, and a memory organization of said memory block is programmably selectable a user-programmable memory bit; and a pad coupled to provide addresses to an address bus of said memory block from an external source to said programmable logic device integrated circuit.

Claim 58

Dependent Claim 24 words

The programmable logic device integrated circuit of claim 52 wherein a word size and a depth size for said memory block are programmably selectable.

Claim 59

Dependent Claim 72 words

The programmable logic device integrated circuit of claim 52 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

Claim 60

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 52 wherein said first plurality of conductors is coupled to an address bus of said memory block.

Claim 61

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 52 wherein said first plurality of conductors is coupled to a data bus of said memory block.

Claim 62

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 52 wherein an output bus of said memory block is coupled to said first plurality of conductors.

Claim 63

Dependent Claim 19 words

The programmable logic device integrated circuit of claim 52 wherein said user-programmable memory bit is a floating gate device.

Claim 64

Dependent Claim 18 words

The programmable logic device integrated circuit of claim 52 wherein said user-programmable memory bit is an antifuse element.

Claim 65

Dependent Claim 18 words

The programmable logic device integrated circuit of claim 52 wherein said user-programmable memory bit is an SRAM cell.

Claim 66

Dependent Claim 31 words

The programmable logic device integrated circuit of claim 52 further comprising: a global clock signal, coupled to at least one of said plurality of logic array blocks and said memory block.

Claim 67

Dependent Claim 19 words

The programmable logic device integrated circuit of claim 52 wherein said programmable logic device is configurable by in-system programming.

Claim 68

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 52 wherein said memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs controls operations of said memory block.

Claim 69

Dependent Claim 44 words

The programmable logic device integrated circuit of claim 52 wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, a plurality of control inputs for said memory block.

Claim 70

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 52 wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block.

Claim 71

Dependent Claim 30 words

The programmable logic device integrated circuit of claim 52 wherein at least one logic element is coupled directly to said memory block without passing through said second plurality of conductors.

Claim 72

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 52 wherein said second plurality of conductors is programmably coupled to said memory block using fully populated multiplexing.

Claim 73

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 52 wherein said second plurality of conductors is programmably coupled to said memory block using partially populated multiplexing.

Claim 74

Dependent Claim 42 words

The programmable logic device integrated circuit of claim 52 further comprising: a crossbar switch, coupled between said memory block and said second plurality of conductors, wherein said second plurality of conductors is programmably coupled to said crossbar switch using partially populated multiplexing.

Claim 75

Dependent Claim 45 words

The programmable logic device integrated circuit of claim 52 further comprising: a plurality of input-output blocks, coupled to said plurality of logic array blocks; and an output enable signal, programmably coupled to at least one of said plurality of input-output blocks and said memory block.

Claim 76

Dependent Claim 35 words

A digital processing system comprising: a processing unit; a memory, coupled to said processing unit; and a programmable logic device integrated circuit as recited in claim 52, coupled to said processing unit and said memory.

Claim 77

Dependent Claim 159 words

A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a memory block, programmably coupled to said first plurality of conductors, and wherein a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors, wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, a plurality of control inputs for said memory block; and a pad coupled to provide addresses to an address bus of said memory block from a source external to said programmable logic device integrated circuit.

Claim 78

Dependent Claim 159 words

A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a memory block, programmably coupled to said first plurality of conductors, and wherein a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors, wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, a plurality of control inputs for said memory block; and a pad coupled to provide addresses to an address bus of said memory block from a source external to said programmable logic device integrated circuit.

Claim 79

Dependent Claim 24 words

The programmable logic device integrated circuit of claim 72 wherein a word size and a depth size for said memory block are programmably selectable.

Claim 80

Dependent Claim 72 words

The programmable logic device integrated circuit of claim 72 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

Claim 81

Dependent Claim 17 words

The programmable logic device integrated circuit of claim 72 wherein said memory block is a single-port memory.

Claim 82

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 72 wherein said first plurality of conductors is coupled to an address bus of said memory block.

Claim 83

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 72 wherein said first plurality of conductors is coupled to a data bus of said memory block.

Claim 84

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 72 wherein an output bus of said memory block is coupled to said first plurality of conductors.

Claim 85

Dependent Claim 19 words

The programmable logic device integrated circuit of claim 72 wherein said user-programmable memory bit is a floating gate device.

Claim 86

Dependent Claim 18 words

The programmable logic device integrated circuit of claim 72 wherein said user-programmable memory bit is an antifuse element.

Claim 87

Dependent Claim 18 words

The programmable logic device integrated circuit of claim 72 wherein said user-programmable memory bit is an SRAM cell.

Claim 88

Dependent Claim 31 words

The programmable logic device integrated circuit of claim 72 further comprising: a global clock signal, coupled to at least one of said plurality of logic array blocks and said memory block.

Claim 89

Dependent Claim 21 words

The programmable logic device integrated circuit of claim 72 wherein said programmable logic device integrated circuit is configurable by in-system programming.

Claim 90

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 72 wherein said memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs controls operations of said memory block.

Claim 91

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 72 wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block.

Claim 92

Dependent Claim 30 words

The programmable logic device integrated circuit of claim 72 wherein at least one logic element is coupled directly to said memory block without passing through said second plurality of conductors.

Claim 93

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 72 wherein said second plurality of conductors is programmably coupled to said memory block using fully populated multiplexing.

Claim 94

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 72 wherein said second plurality of conductors is programmably coupled to said memory block using partially populated multiplexing.

Claim 95

Dependent Claim 42 words

The programmable logic device integrated circuit of claim 72 further comprising: a crossbar switch, coupled between said memory block and said second plurality of conductors, wherein said second plurality of conductors is programmably coupled to said crossbar switch using partially populated multiplexing.

Claim 96

Dependent Claim 45 words

The programmable logic device integrated circuit of claim 72 further comprising: a plurality of input-output blocks, coupled to said plurality of logic array blocks; and an output enable signal, programmably coupled to at least one of said plurality of input-output blocks and said memory block.

Claim 97

Dependent Claim 35 words

A digital processing system comprising: a processing unit; a memory, coupled to said processing unit; and a programmable logic device integrated circuit as recited in claim 72, coupled to said processing unit and said memory.

Claim 98

Dependent Claim 155 words

A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; a memory block, programmably coupled to said first plurality of conductors, wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block and, wherein a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; and a pad coupled to provide addresses to an address bus of said memory block from a source external to said programmable logic device integrated circuit.

Claim 99

Dependent Claim 155 words

A programmable logic device integrated circuit comprising: a first plurality of conductors, extending along a first dimension of a two-dimensional array; a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors; a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors; a memory block, programmably coupled to said first plurality of conductors, wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block and, wherein a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; and a pad coupled to provide addresses to an address bus of said memory block from a source external to said programmable logic device integrated circuit.

Claim 100

Dependent Claim 24 words

The programmable logic device integrated circuit of claim 92 wherein a word size and a depth size for said memory block are programmably selectable.

Claim 101

Dependent Claim 72 words

The programmable logic device integrated circuit of claim 92 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

Claim 102

Dependent Claim 17 words

The programmable logic device integrated circuit of claim 92 wherein said memory block is a single-port memory.

Claim 103

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 92 wherein said first plurality of conductors is coupled to an address bus of said memory block.

Claim 104

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 92 wherein said first plurality of conductors is coupled to a data bus of said memory block.

Claim 105

Dependent Claim 25 words

The programmable logic device integrated circuit of claim 92 wherein an output bus of said memory block is coupled to said first plurality of conductors.

Claim 106

Dependent Claim 19 words

The programmable logic device integrated circuit of claim 92 wherein said user-programmable memory bit is a floating gate device.

Claim 107

Dependent Claim 18 words

The programmable logic device integrated circuit of claim 92 wherein said user-programmable memory bit is an antifuse element.

Claim 108

Dependent Claim 18 words

The programmable logic device integrated circuit of claim 92 wherein said user-programmable memory bit is an SRAM cell.

Claim 109

Dependent Claim 31 words

The programmable logic device integrated circuit of claim 92 further comprising: a global clock signal, coupled to at least one of said plurality of logic array blocks and said memory block.

Claim 110

Dependent Claim 19 words

The programmable logic device integrated circuit of claim 92 wherein said programmable logic device is configurable by in-system programming.

Claim 111

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 92 wherein said memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs controls operations of said memory block.

Claim 112

Dependent Claim 30 words

The programmable logic device integrated circuit of claim 92 wherein at least one logic element is coupled directly to said memory block without passing through said second plurality of conductors.

Claim 113

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 92 wherein said second plurality of conductors is programmably coupled to said memory block using fully populated multiplexing.

Claim 114

Dependent Claim 26 words

The programmable logic device integrated circuit of claim 92 wherein said second plurality of conductors is programmably coupled to said memory block using partially populated multiplexing.

Claim 115

Dependent Claim 42 words

The programmable logic device integrated circuit of claim 92 further comprising: a crossbar switch, coupled between said memory block and said second plurality of conductors, wherein said second plurality of conductors is programmably coupled to said crossbar switch using partially populated multiplexing.

Claim 116

Dependent Claim 45 words

The programmable logic device integrated circuit of claim 92 further comprising: a plurality of input-output blocks, coupled to said plurality of logic array blocks; and an output enable signal, programmably coupled to at least one of said plurality of input-output blocks and said memory block.

Claim 117

Dependent Claim 35 words

A digital processing system comprising: a processing unit; a memory, coupled to said processing unit; and a programmable logic device integrated circuit as recited in claim 92, coupled to said processing unit and said memory.

Claim 118

Dependent Claim 86 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and a memory block programmably coupled to said programmable interconnect array, wherein said memory block is dual-ported and comprises: a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and an address bus accessible from a second pad.

Claim 119

Dependent Claim 86 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and a memory block programmably coupled to said programmable interconnect array, wherein said memory block is dual-ported and comprises: a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and an address bus accessible from a second pad.

Claim 120

Dependent Claim 26 words

The programmable logic integrated circuit of claim 111 wherein accessibility to said data bus from said programmable interconnect array or said first pad is programmably configurable.

Claim 121

Dependent Claim 26 words

The programmable logic integrated circuit of claim 114 wherein concurrent access to said memory block from said programmable interconnect array and said first pad is permitted.

Claim 122

Dependent Claim 19 words

The programmable logic integrated circuit of claim 111 wherein said address bus is accessible from said programmable interconnect array.

Claim 123

Dependent Claim 32 words

The programmable logic integrated circuit of claim 111 wherein said memory block further comprises: an output bus, programmably configurable to provide data output to said programmable interconnect array or a third pad.

Claim 124

Dependent Claim 23 words

The programmable logic integrated circuit of claim 115 wherein said output bus is programmably coupled to provide data output to said data bus.

Claim 125

Dependent Claim 40 words

The programmable logic integrated circuit of claim 111 wherein said memory block further comprises: a plurality of control inputs to control operation of said memory block, wherein said plurality of control inputs is programmably coupled to the programmable interconnect array.

Claim 126

Dependent Claim 34 words

The programmable logic integrated circuit of claim 111 wherein said memory block further comprises: a busy flag signal to indicate whether a read port and a write port are addressing a similar memory location.

Claim 127

Dependent Claim 37 words

The programmable logic integrated circuit of claim 111 wherein said memory block further comprises: a first portion of memory cells; and a second portion of memory cells, wherein said first and second portions are coupled in parallel.

Claim 128

Dependent Claim 27 words

The programmable logic integrated circuit of claim 111 wherein a memory organization of said memory block is programmably configurable by using at least one user-programmable memory cell.

Claim 129

Dependent Claim 72 words

The programmable logic device integrated circuit of claim 120 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

Claim 130

Dependent Claim 103 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and a memory block programmably coupled to said programmable interconnect array, said memory block comprising: a busy flag signal to indicate whether a read port and a write port are addressing a similar memory location; and a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and an address bus accessible from a second pad.

Claim 131

Dependent Claim 103 words

A programmable logic integrated circuit comprising: a plurality of logic elements configurable to perform logical functions; a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and a memory block programmably coupled to said programmable interconnect array, said memory block comprising: a busy flag signal to indicate whether a read port and a write port are addressing a similar memory location; and a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and an address bus accessible from a second pad.

Claim 132

Dependent Claim 26 words

The programmable logic integrated circuit of claim 122 wherein accessibility to said data bus from said programmable interconnect array or said first pad is programmably configurable.

Claim 133

Dependent Claim 26 words

The programmable logic integrated circuit of claim 122 wherein concurrent access to said memory block from said programmable interconnect array and said first pad is permitted.

Claim 134

Dependent Claim 19 words

The programmable logic integrated circuit of claim 122 wherein said address bus is accessible from said programmable interconnect array.

Claim 135

Dependent Claim 32 words

The programmable logic integrated circuit of claim 122 wherein said memory block further comprises: an output bus, programmably configurable to provide data output to said programmable interconnect array or a third pad.

Claim 136

Dependent Claim 23 words

The programmable logic integrated circuit of claim 126 wherein said output bus is programmably coupled to provide data output to said data bus.

Claim 137

Dependent Claim 14 words

The programmable logic integrated circuit of claim 122 wherein said memory block is single-ported.

Claim 138

Dependent Claim 40 words

The programmable logic integrated circuit of claim 122 wherein said memory block further comprises: a plurality of control inputs to control operation of said memory block, wherein said plurality of control inputs is programmably coupled to the programmable interconnect array.

Claim 139

Dependent Claim 37 words

The programmable logic integrated circuit of claim 122 wherein said memory block further comprises: a first portion of memory cells; and a second portion of memory cells, wherein said first and second portions are coupled in parallel.

Claim 140

Dependent Claim 27 words

The programmable logic integrated circuit of claim 122 wherein a memory organization of said memory block is programmably configurable by using at least one user-programmable memory cell.

Claim 141

Dependent Claim 72 words

The programmable logic device integrated circuit of claim 131 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

Claim 142

Dependent Claim 37 words

The programmable logic device integrated circuit of claim 1 wherein said pad is directly coupled to said address bus of said memory block, without passing through said first plurality of conductors and said second plurality of conductors.

Claim 143

Dependent Claim 38 words

The programmable logic device integrated circuit of claim 1 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Claim 144

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 16 wherein the plurality of flag outputs includes an ALMOST FULL flag output indicating that said memory block has a specified number of unoccupied memory locations, the specified number being user programmable.

Claim 145

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 16 wherein the plurality of flag outputs includes an ALMOST EMPTY flag output indicating that said memory block has a specified number of occupied memory locations, the specified number being user programmable.

Claim 146

Dependent Claim 39 words

The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Claim 147

Dependent Claim 43 words

The programmable logic integrated circuit of claim 23 further comprising a pad coupled to an address bus of said first-in, first-out memory block for providing addresses to said programmable logic integrated circuit from an external source without passing through said programmable interconnect array.

Claim 148

Dependent Claim 19 words

The programmable logic integrated circuit of claim 23 wherein said user-programmable memory bit is a floating point gate device.

Claim 149

Dependent Claim 17 words

The programmable logic integrated circuit of claim 23 wherein said user-programmable memory bit is an antifuse element.

Claim 150

Dependent Claim 17 words

The programmable logic integrated circuit of claim 23 wherein said user-programmable memory bit is a SRAM cell.

Claim 151

Dependent Claim 26 words

The programmable logic integrated circuit of claim 36 wherein said second pad is directly coupled to said address bus, without passing through said programmable interconnect array.

Claim 152

Dependent Claim 37 words

The programmable logic integrated circuit of claim 36 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Claim 153

Dependent Claim 26 words

The programmable logic integrated circuit of claim 49 wherein said first pad is directly coupled to said address bus without passing through said programmable interconnect array.

Claim 154

Dependent Claim 37 words

The programmable logic integrated circuit of claim 49 wherein said memory module is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation mode being user selectable.

Claim 155

Dependent Claim 37 words

The programmable logic device integrated circuit of claim 52 wherein said pad is directly coupled to said address bus of said memory block, without passing through said first plurality of conductors and said second plurality of conductors.

Claim 156

Dependent Claim 38 words

The programmable logic device integrated circuit of claim 52 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Claim 157

Dependent Claim 39 words

The programmable logic device integrated circuit of claim 65 wherein plurality of flag outputs includes an ALMOST FULL flag output indicating that said memory block has a specified number of unoccupied memory locations, the specified number being user programmable.

Claim 158

Dependent Claim 39 words

The programmable logic device integrated circuit of claim 65 wherein plurality of flag outputs includes an ALMOST EMPTY flag output indicating that said memory block has a specified number of occupied memory locations, the specified number being user programmable.

Claim 159

Dependent Claim 37 words

The programmable logic device integrated circuit of claim 72 wherein said pad is directly coupled to said address bus of said memory block, without passing through said first plurality of conductors and said second plurality of conductors.

Claim 160

Dependent Claim 38 words

The programmable logic device integrated circuit of claim 72 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Claim 161

Dependent Claim 39 words

The programmable logic device integrated circuit of claim 85 wherein plurality of flag outputs includes an ALMOST FULL flag output indicating that said memory block has a specified number of unoccupied memory locations, the specified number being user programmable.

Claim 162

Dependent Claim 39 words

The programmable logic device integrated circuit of claim 85 wherein plurality of flag outputs includes an ALMOST EMPTY flag output indicating that said memory block has a specified number of occupied memory locations, the specified number being user programmable.

Claim 163

Dependent Claim 37 words

The programmable logic device integrated circuit of claim 92 wherein said pad is directly coupled to said address bus of said memory block, without passing through said first plurality of conductors and said second plurality of conductors.

Claim 164

Dependent Claim 38 words

The programmable logic device integrated circuit of claim 92 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Claim 165

Dependent Claim 26 words

The programmable logic integrated circuit of claim 111 wherein said second pad is directly coupled to said address bus, without passing through said programmable interconnect array.

Claim 166

Dependent Claim 37 words

The programmable logic integrated circuit of claim 111 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Claim 167

Dependent Claim 26 words

The programmable logic integrated circuit of claim 122 wherein said second pad is directly coupled to said address bus, without passing through said programmable interconnect array.

Claim 168

Dependent Claim 37 words

The programmable logic integrated circuit of claim 122 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Claim 169

Dependent Claim 168 words

A programmable logic device integrated circuit comprising: means for programmably conducting logic signals along a first dimension of a two-dimension array; means for programmably conducting logic signal along a second dimension of said two-dimensional array, said means for programmably conducting said logic signals along said second dimension being programmably coupled to said means for programmably conducting said logic signals along said first dimension; means for programmably implementing logical functions coupled to said means for programmably conducting said logic signals along said second dimension and said means for programmably conducting said logic signals along said first dimension; means for storing data coupled to said means for programmably conducting said logic signals along said first dimension; means for programmably configuring said means for storing data as a random access memory in a first mode and as a first-in, first-out memory in a second mode; and means for providing addresses to an address bus of said means for storing data from a source external to said programmable logic device integrated circuit.

Claim 170

Dependent Claim 168 words

A programmable logic device integrated circuit comprising: means for programmably conducting logic signals along a first dimension of a two-dimension array; means for programmably conducting logic signal along a second dimension of said two-dimensional array, said means for programmably conducting said logic signals along said second dimension being programmably coupled to said means for programmably conducting said logic signals along said first dimension; means for programmably implementing logical functions coupled to said means for programmably conducting said logic signals along said second dimension and said means for programmably conducting said logic signals along said first dimension; means for storing data coupled to said means for programmably conducting said logic signals along said first dimension; means for programmably configuring said means for storing data as a random access memory in a first mode and as a first-in, first-out memory in a second mode; and means for providing addresses to an address bus of said means for storing data from a source external to said programmable logic device integrated circuit.

Claim 171

Dependent Claim 57 words

The programmable logic device integrated circuit of claim 160 wherein said means for providing said addresses is directly coupled to said address bus of said means for storing data, without passing through said means for programmably conducting said logic signals along said second dimension and said means for programmably said conducting logic signals along said first dimension.

Claim 172

Dependent Claim 40 words

The programmable logic device integrated circuit of claim 160 wherein said means for storing data is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2003-04-11	2003-10-11	2004-04-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2007-04-11	2007-10-11	2008-04-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2011-04-11	2011-10-11	2012-04-11	$7700.00	Window Closed / Lapsed

Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory

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